XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 147

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Built-in FIFO Support
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
A large percentage of FPGA designs use block RAMs to implement FIFOs. In the Virtex-4
architecture, dedicated logic in the block RAM enables users to easily implement
synchronous or asynchronous FIFOs. This eliminates the need for additional CLB logic for
counter, comparator, or status flag generation, and uses just one block RAM resource per
FIFO. Both standard and first-word fall-through (FWFT) modes are supported.
The supported configurations are 4K x 4, 2K x 9, 1K x 18, and 512 x 36.
The block RAM can be configured as first-in/first-out (FIFO) memory with common or
independent read and write clocks. Port A of the block RAM is used as a FIFO read port,
and Port B is a FIFO write port. Data is read from the FIFO on the rising edge of read clock
and written to the FIFO on the rising edge of write clock. Independent read and write port
width selection is not supported in FIFO mode without the aid of external CLB logic.
The FIFO offers a very simple user interface. The design relies on free-running write and
read clocks, of identical or different frequencies up to the specified maximum frequency
limit. The design avoids any ambiguity, glitch, or metastable problems, even when the two
frequencies are completely unrelated.
The write operation is synchronous, writing the data word available at DI into the FIFO
whenever WREN is active a setup time before the rising WRCLK edge.
The read operation is also synchronous, presenting the next data word at DO whenever the
RDEN is active one setup time before the rising RDCLK edge.
Data flow control is automatic; the user need not be concerned about the block RAM
addressing sequence, although WRCOUNT and RDCOUNT are also brought out, if
needed for unusual applications.
The user must, however, observe the FULL and EMPTY flags, and stop writing when
FULL is High, and stop reading when EMPTY is High. If these rules are violated, an active
WREN while FULL is High will activate the WRERR flag, and an active RDEN while
EMPTY is High will activate the RDERR flag. In either violation, the FIFO content will,
however, be preserved, and the address counters will stay valid.
Write Enable
Synchronous
Set/Reset
Address
Enable
Clock
Data
[T
[T
[T
[T
IOPI
[T
[T
IOPI
IOPI
IOPI
IOPI
IOPI
+ NET]
+ NET] + T
Figure 4-13: Block RAM Timing Model
+ NET] + T
+ NET] + T
+ NET] + T
[T
+ NET] + T
www.xilinx.com
BCCKO_O
BUFGCTRL
RCCK_ADDR
RCCK_WEN
RCCK_SSR
RCCK_EN
RDCK_DI
+ NET]
DI
ADDR
WEN
EN
SSR
CLK
Block RAM
FPGA
DO
T
RCKO_DO
Built-in FIFO Support
+ [NET + T
IOOP
ug070_4_13_080204
]
Data
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