XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 349

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
The VHDL and Verilog use models for instantiating a mixed usage model are provided. In
the example, a user is instantiating a non-location constrained IDELAYCTRL instance with
the RDY signal connected. This discussion is also valid when the RDY signal is ignored.
VHDL Use Model
-- Multiple instantiations of IDELAYCTRL primitives with LOC
-- constraints.
-- Each instance has its own RST and RDY signal to allow for partial
-- reconfiguration.
-- The REFCLK signal is common to all instances (LOC and replicated
-- instances)
dlyctrl_1:IDELAYCTRL
dlyctrl_2:IDELAYCTRL
.
.
.
dlyctrl_n:IDELAYCTRL
-- The user should either declare the LOC constraints in the
-- VHDL design file or in the UCF file.
-- Declaring LOC constraints in the VHDL file.
attribute loc : string;
attribute loc of dlyctrl_1:label is "IDELAYCTRL_X0Y0";
attribute loc of dlyctrl_2:label is "IDELAYCTRL_X0Y1";
.
.
.
attribute loc of dlyctrl_n:label is "IDELAYCTRL_XnYn";
-- Declaring LOC constraints in the UCF file:
INST "dlyctrl_1" LOC=IDELAYCTRL_X0Y0;
INST "dlyctrl_2" LOC=IDELAYCTRL_X0Y1;
.
.
.
INST "dlyctrl_n" LOC=IDELAYCTRL_XnYn;
-- One instantiation of an IDELAYCTRL primitive without LOC constraint
-- RST and RDY port signals are independent from LOC-ed instances
dlyctrl_noloc:IDELAYCTRL
port map(
port map(
port map(
port map(
www.xilinx.com
);
);
);
);
RDY => rdy _1,
REFCLK => refclk,
RST => rst_1
RDY => rdy _2,
REFCLK => refclk,
RST => rst_2
RDY => rdy _n,
REFCLK => refclk,
RST => rst_n
RDY => rdy_noloc,
REFCLK => refclk,
RST => rst_noloc
ILOGIC Resources
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