XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 247

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
IBUF and IBUFG
OBUF
OBUFT
R
These five generic primitive names represent most of the available differential I/O
standards:
•
•
•
•
•
Signals used as inputs to Virtex-4 devices must use an input buffer (IBUF). The generic
Virtex-4 FPGA IBUF primitive is shown in
The IBUF and IBUFG primitives are the same. IBUFGs are used when an input buffer is
used as a clock input. In the Xilinx software tools, an IBUFG is automatically placed at
clock input sites.
An output buffer (OBUF) must be used to drive signals from Virtex-4 devices to external
output pads. A generic Virtex-4 FPGA OBUF primitive is shown in
The generic 3-state output buffer OBUFT, shown in
3-state outputs or bidirectional I/O.
IBUFDS (input buffer)
IBUFGDS (clock input buffer)
OBUFDS (output buffer)
OBUFTDS (3-state output buffer)
IOBUFDS (input/output buffer)
Figure 6-19: 3-State Output Buffer (OBUFT) Primitive
Figure 6-17: Input Buffer (IBUF/IBUFG) Primitives
Figure 6-18: Output Buffer (OBUF) Primitive
From Device Pad
From FPGA
3-state input
From FPGA
I (Input)
I (Input)
www.xilinx.com
I (Input)
T
OBUFT
OBUF
IBUF/IBUFG
Figure
6-17.
Figure
Virtex-4 FPGA SelectIO Primitives
O (Output)
to Device Pad
UG070_6_19_031108
O (Output)
to Device Pad
UG070_6_18_031108
UG070_6_17_031108
6-19, typically implements
O (Output)
into FPGA
Figure
6-18.
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