XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 223

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Initialization in VHDL or Verilog Code
Port Signals
R
Clock - CLK
Data In - D
Clock Enable - CE (optional)
Address - A0, A1, A2, A3
Data Out - Q
Data Out - Q15 (optional)
Inverting Control Pins
Global Set/Reset - GSR
A shift register can be initialized in VHDL or Verilog code for both synthesis and
simulation. For synthesis, the attribute is attached to the 16-bit shift register instantiation
and is copied in the EDIF output file to be compiled by Xilinx Alliance Series tools. The
VHDL code simulation uses a generic parameter to pass the attributes. The Verilog code
simulation uses a defparam parameter to pass the attributes.
The Virtex-4_SRL16E shift register instantiation code examples (in VHDL and Verilog)
illustrate these techniques
and Virtex-4_SRL16E.v files are not a part of the documentation.
Either the rising edge or the falling edge of the clock is used for the synchronous shift
operation. The data and clock enable input pins have setup times referenced to the chosen
edge of CLK.
The data input provides new data (one bit) to be shifted into the shift register.
The clock enable pin affects shift functionality. An inactive clock enable pin does not shift
data into the shift register and does not write new data. Activating the clock enable allows
the data in (D) to be written to the first location and all data to be shifted by one location.
When available, new data appears on output pins (Q) and the cascadable output pin (Q15).
Address inputs select the bit (range 0 to 15) to be read. The nth bit is available on the output
pin (Q). Address inputs have no effect on the cascadable output pin (Q15); it is always the
last bit of the shift register (bit 15).
The data output Q provides the data value (1 bit) selected by the address inputs.
The data output Q15 provides the last bit value of the 16-bit shift register. New data
becomes available after each shift-in operation.
The two control pins (CLK, CE) have an individual inversion option. The default is the
rising clock edge and active High clock enable.
The global set/reset (GSR) signal has no impact on shift registers.
Shift Registers (SRLs) Primitives and Verilog/VHDL Example
www.xilinx.com
(“VHDL and Verilog
Templates”). Virtex-4_SRL16E.vhd
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