XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 378

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 8: Advanced SelectIO Logic Resources
378
// synthesis IOBDELAY_VALUE of data_chan_master is
// synthesis NUM_CE of data_chan_master is
// synthesis SERDES_MODE of data_chan_master is
//
// Instantiate Slave ISERDES for data channel
// 1:10 Deserialization Factor
ISERDES data_chan_slave (
// synthesis BITSLIP_ENABLE of data_chan_slave is
// synthesis DATA_RATE of data_chan_slave is
// synthesis DATA_WIDTH of data_chan_slave is
// synthesis INTERFACE_TYPE of data_chan_slave is "NETWORKING";
// synthesis IOBDELAY of data_chan_slave is
// synthesis IOBDELAY_TYPE of data_chan_slave is
// synthesis IOBDELAY_VALUE of data_chan_slave is
// synthesis NUM_CE of data_chan_slave is
// synthesis SERDES_MODE of data_chan_slave is
//
BUFIO bufio1 (
// To get a 1:10 deserialization factor in DDR mode,
// set the clock divide factor to "5"
BUFR bufr1 (
// synthesis BUFR_DIVIDE of bufr1 is
endmodule
.O(clkdiv),
.CE(1'b1),
.CLR(1'b0),
.I(iobclk)
);
);
.O(iobclk),
.I(iserdes_clkout)
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.O(),
.Q1(),
.Q2(),
.Q3(data_internal[6]),
.Q4(data_internal[7]),
.Q5(data_internal[8]),
.Q6(data_internal[9]),
.SHIFTOUT1(),
.SHIFTOUT2(),
.BITSLIP(1'b0),
.CE1(1'b1),
.CE2(1'b1),
.CLK(iobclk),
.CLKDIV(clkdiv),
.D(1'b0),
.DLYCE(1'b0),
.DLYINC(1'b0),
.DLYRST(1'b0),
.OCLK(1'b0),
.REV(1'b0),
.SHIFTIN1(shiftdata1),
.SHIFTIN2(shiftdata2),
.SR(rst),
);
"5";
1;
1;
"NONE";
UG070 (v2.6) December 1, 2008
"DDR";
10;
"SLAVE";
"MASTER";
Virtex-4 FPGA User Guide
"DEFAULT";
"TRUE";
0;
0;
R