XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 170

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 4: Block RAM
170
FASTCLK
WRCLK
RDCLK
WREN
RDEN
RST
Solution 2: Work-Around Using a Third Fast Clock
Design Description
D
CE
D
CE
D
CE
D
CE
If the frequencies of WRCLK and RDCLK are low enough, it is possible to synchronize
FIFO reads and writes to a third asynchronous fast clock (FASTCLK). The ALMOSTFULL
and ALMOSTEMPTY flags are generated in this fast clock domain. These flags are then
resynchronized to their respective clocks.
The system described in this solution requires a minimum of 2 and a maximum of 3 fast
clock cycles to process a single read or write cycle. To handle back-to-back read or writes,
the fast process must complete within one RDCLK or WRCLK period. Thus, the fast clock
must be at least three times faster than the faster of WRCLK and RDCLK.
For example, if the fastest RDCLK or WRCLK is 125 MHz, then FASTCLK could be
400 MHz (400/125 = 3.2).
The circuit shown in
Up/Down counter must be large enough to hold the maximum number of words in the
FIFO; e.g., 10 bits wide if the FIFO depth is 512 words.
The WIF signal is used along with the ALMOST_EMPTY_OFFSET to generate the
ALMOST_FULL and ALMOST_EMPTY flags, as shown in
RST
RST
RST
RST
Q
Q
Q
Q
Figure 4-27: WIF Signal Generation
Wr
Rd
Figure 4-27
www.xilinx.com
D
D
RST
RST
is used to generate the “words in FIFO” (WIF) signal. The
Q
Q
WM
RM
Write
Read
D
D
RST
RST
Q
Q
Figure
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
Words in FIFO
4-28.
INC
CE
UP/DOWN
CNTR[9:0]
RST
CNTR
UG070_c4_28_020607
WIF[9:0]
R