XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 332

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 7: SelectIO Logic Resources
332
IDELAY Primitive
•
•
•
Figure 7-11
Table 7-6
Table 7-6: IDELAY Primitive
Name
Port
INC
RST
CE
O
Zero-hold time delay mode (IOBDELAY_TYPE = DEFAULT)
This mode of operation allows backward compatibility for designs using the zero-hold
time delay feature in Virtex-II and Virtex-II Pro devices. When used in this mode, the
IDELAYCTRL primitive does not need to be instantiated (see
Design Guidelines
Fixed delay mode (IOBDELAY_TYPE = FIXED)
In the fixed delay mode, the delay value is preset at configuration to the tap number
determined by the attribute IOBDELAY_VALUE. Once configured, this value cannot
be changed. When used in this mode, the IDELAYCTRL primitive must be instantiated
(see
Variable delay mode (IOBDELAY_TYPE = VARIABLE)
In the variable delay mode, the delay value can be changed after configuration by
manipulating the control signals CE and INC. When used in this mode, the
IDELAYCTRL primitive must be instantiated (see
Guidelines
C
I
IDELAYCTRL Usage and Design Guidelines
lists the available ports in the IDELAY primitive.
Direction
shows the IDELAY primitive.
Output
Input
Input
Input
Input
Input
for more details).
Serial input data from IOB
Clock input when in Variable mode
Increment/decrement number of tap delays when in Variable mode
Enable increment/decrement function when in Variable mode
Reset delay element to pre-programmed value. If no value
programmed, reset to 0.
Combinatorial output
for more details).
www.xilinx.com
Figure 7-11: IDELAY Primitive
I
INC
RST
CE
C
IDELAY
ug070_7_11_080104
O
Function
for more details).
IDELAYCTRL Usage and Design
UG070 (v2.6) December 1, 2008
IDELAYCTRL Usage and
Virtex-4 FPGA User Guide
R