XC4VFX60-11FFG672I Xilinx Inc, XC4VFX60-11FFG672I Datasheet - Page 397

• Manufacturer Part Number: XC4VFX60-11FFG672I
• Description: IC FPGA VIRTEX-4 FX 60K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-11FFG672I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Clock Event 1
T1, T2, and T4 are driven Low to release the 3-state condition. The serialization paths of
T1–T4 and D1–D4 in the OSERDES are identical (including latency), such that the bits
EFGH are always aligned with the 0010 presented at the T1–T4 pins during Clock Event 1.
Clock Event 2
The data bit E appears at OQ one CLK cycle after EFGH is sampled into the OSERDES. This
latency is consistent with
DDR mode is one CLK cycle.
The 3-state bit 0 at T1 during Clock Event 1 appears at TQ one CLK cycle after 0010 is
sampled into the OSERDES 3-state block. This latency is consistent with
states that the latency of an OSERDES in 4:1 DDR mode is one CLK cycle.
OBUFT.O
CLKDIV
CLK
OQ
TQ
D1
D2
D3
D4
Figure 8-20: 3-State Control Serialization in 4:1 DDR Mode
T1
T2
T3
T4
Table
www.xilinx.com
1
1
1
1
C
D
A
B
8-11, which states that the latency of an OSERDES in 4:1
Output Parallel-to-Serial Logic Resources (OSERDES)
Event 1
Clock
A B C D E F G H
G
H
E
F
0
0
1
0
Clock
Event 2
E F
K
L
J
I
H
I J K L
1
1
1
1
UG070_c8_27_041007
Table
8-11, which
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