LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 5

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
LatticeXP2 sysCLOCK PLL Design and Usage Guide
Differential I/O Implementation......................................................................................................................... 8-11
Technical Support Assistance.......................................................................................................................... 8-11
Revision History ............................................................................................................................................... 8-11
Appendix A. HDL Attributes for Synplicity
Appendix B. sysIO Attributes Using the Design Planner User Interface .......................................................... 8-16
Appendix C. sysIO Attributes Using Preference File (ASCII File) .................................................................... 8-17
Introduction ........................................................................................................................................................ 9-1
Clock/Control Distribution Network .................................................................................................................... 9-1
LatticeXP2 Top Level View ................................................................................................................................ 9-1
Primary Clocks ................................................................................................................................................... 9-2
Secondary Clocks .............................................................................................................................................. 9-2
Edge Clocks ....................................................................................................................................................... 9-2
Primary Clock Note ............................................................................................................................................ 9-3
Specifying Clocks in the Design Tools ............................................................................................................... 9-3
Global Primary Clock and Quadrant Primary Clock ........................................................................................... 9-3
sysCLOCK™ PLL .............................................................................................................................................. 9-4
Functional Description........................................................................................................................................ 9-5
PLL Inputs and Outputs ..................................................................................................................................... 9-5
PLL Attributes..................................................................................................................................................... 9-7
LatticeXP2 PLL Primitive Definition.................................................................................................................... 9-8
LVDS....................................................................................................................................................... 8-11
BLVDS .................................................................................................................................................... 8-11
RSDS ...................................................................................................................................................... 8-11
LVPECL .................................................................................................................................................. 8-11
Differential SSTL and HSTL.................................................................................................................... 8-11
MLVDS.................................................................................................................................................... 8-11
VHDL Synplicity/Precision RTL Synthesis .............................................................................................. 8-12
Verilog Synplicity..................................................................................................................................... 8-14
Verilog Precision ..................................................................................................................................... 8-15
IOBUF ..................................................................................................................................................... 8-17
LOCATE.................................................................................................................................................. 8-17
USE DIN CELL........................................................................................................................................ 8-18
USE DOUT CELL.................................................................................................................................... 8-18
GROUP VREF ........................................................................................................................................ 8-18
Primary-Pure and Primary-DCS................................................................................................................ 9-3
Global Primary Clock ................................................................................................................................ 9-3
Quadrant Primary Clock............................................................................................................................ 9-4
PLL Divider and Delay Blocks................................................................................................................... 9-5
CLKI Input ................................................................................................................................................. 9-5
RST Input .................................................................................................................................................. 9-5
RSTK Input................................................................................................................................................ 9-6
CLKFB Input.............................................................................................................................................. 9-6
CLKOP Output .......................................................................................................................................... 9-6
CLKOS Output with Phase and Duty Cycle Select ................................................................................... 9-6
CLKOK Output with Lower Frequency ...................................................................................................... 9-6
CLKOK2 Output ........................................................................................................................................ 9-6
LOCK Output............................................................................................................................................. 9-6
Dynamic Phase and Dynamic Duty Cycle Adjustment.............................................................................. 9-6
WRDEL (Write Delay) ............................................................................................................................... 9-7
FIN ............................................................................................................................................................ 9-7
CLKI_DIV, CLKFB_DIV, CLKOP_DIV, CLKOK_DIV ................................................................................ 9-7
FREQUENCY_PIN_CLKI, FREQUENCY_PIN_CLKOP, FREQUENCY_PIN_CLKOK ............................ 9-7
CLKOP Frequency Tolerance ................................................................................................................... 9-7
®
and Precision
4
®
RTL Synthesis...................................................... 8-12
LatticeXP2 Family Handbook
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