LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 331

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 17-5. Procedure for Program a JEDEC File into the LatticeXP2 using ispVM
Steps
1
2
3
Scan or select the LatticeXP2 device.
Select the Flash Programming Mode under the Device Access Options.
Select the Flash Programming operation from the operation list:
(Note: Due to the operations describe here are all carried out on the JTAG port, as previously noted, the
PROGRAMN pin function is disabled by any activities on the JTAG port, power cycling the LatticeXP2 device
is the only way to re-enable the PROGRAMN pin.)
Flash Background Oper-
ation
FLASH Erase,Pro-
gram,Verify
FLASH Erase,Pro-
gram,Verify,Secure
FLASH Erase,Pro-
gram,Verify,Refresh
FLASH Verify Only
FLASH Erase Only
FLASH Read Status
Register
FLASH Read DONE bit
FLASH Refresh
Comments
This is a Direct Mode operation. The LatticeXP2 device will be forced into an
erased state, by clearing (erase) the SRAM fuses, before and while programming
the embedded Flash. A post programming verification of the Flash fuses is per-
formed. If all of the Flash fuses match the data in the JEDEC file, the Flash Done
fuse is programmed. The pattern from embedded Flash device into the SRAM
fuses using the JTAG ISC_DISABLE instructions at the end of the operation.
This is a Direct Mode operation. The LatticeXP2 device will be forced into an
erased state, by clearing (erase) the SRAM fuses, before and while programming
the embedded Flash. A post programming verification of the Flash fuses is per-
formed. If all of the Flash fuses match the data in the JEDEC file, the Flash Secu-
rity and Done fuses are programmed. The pattern from embedded Flash device
into the SRAM fuses using the JTAG ISC_DISABLE instructions at the end of the
operation.
This is a Direct Mode operation. The LatticeXP2 device will be forced into an
erased state, by clearing (erase) the SRAM fuses, before and while programming
the embedded Flash. A post programming verification of the Flash fuses is per-
formed. If all of the Flash fuses match the data in the JEDEC file, the Flash Done
fuse is programmed. This operation loads the pattern from embedded Flash
device into the SRAM fuses using the JTAG Refresh instruction.
This is a Direct Mode operation. The LatticeXP2 device will be forced into an
erased state, by clearing (erase) the SRAM fuses, before and while programming
the embedded Flash. A verification of the Flash fuses is performed. If all of the
Flash fuses match the data in the JEDEC file, the Flash Done fuse is pro-
grammed. The pattern from embedded Flash device into the SRAM fuses using
the JTAG ISC_DISABLE instructions at the end of the operation.
This is a Direct Mode operation. The LatticeXP2 device will be forced into an
erased state, by clearing (erase) the SRAM fuses, before and while erasing the
embedded Flash. Since the Flash Done bit is erased, the Flash to SRAM transfer
does not happen, and the device remains in the unprogrammed mode. If dual
boot configuration mode is selected, and the golden is located in the external SPI
Flash, the device will configure from the golden pattern contained in the external
SPI Flash device.
This is a Direct Mode operation. The LatticeXP2 device will enter programming
mode while the device Status Register is read and displayed.
This is a Direct Mode operation. The LatticeXP2 device will enter programming
mode while the Flash Done Bit is read and displayed.
This is a Direct Mode operation. This operation loads the pattern from embedded
Flash device into the SRAM fuses using the JTAG Refresh instruction. The
LatticeXP2 device will be forced into an erased state, by clearing (erase) the
SRAM fuses, before and during the Flash to SRAM transfer.
Description
17-13
LatticeXP2 Dual Boot Feature