LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 320

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Complementing its internal Flash configuration memory, the LatticeXP2™ also provides support for inexpensive
SPI Flash devices. This provides the ability to use an alternate or backup bitstream, referred to as the “golden”
image. The device always attempts to load the primary image from the selected source. Should any unexpected
interrupts occur during configuration of the primary image, the LatticeXP2 device will automatically switch sources
and configure from the golden image location.
Dual Boot Feature
One of the biggest risks in the field upgrade applications is disruption during the field grade process. Examples:
To eliminate the risk completely, the device will automatically switch to load from the second known good (Golden)
pattern when the first pattern is corrupted. This is the Dual Boot feature. Thus, the main purpose of the Dual Boot
feature is to enhance the reliability of a field upgradeable system.
The LatticeXP2 devices are known as non-volatile devices for the device has an embedded Flash block storing the
configuration pattern. The advantage of a non-volatile device is the extremely fast instant-on time, made possible
by the massive parallel loading from the embedded Flash into the SRAM block of the device.
To keep the cost as low as possible, the LatticeXP2 only has enough embedded Flash to store one pattern. To
enable the dual boot feature, Lattice designed into the LatticeXP2 device family the popular SPI Flash interface
found originally in the LatticeECP/2/3 family of volatile FPGA devices. The SPI Flash device can be used to store
the second (Golden) pattern.
The basic connections for the two Dual Boot options are shown in Figure 17-2.
Figure 17-2. Dual Boot Options
The Dual Boot feature on the LatticeXP2 devices is designed to be simple for users by carrying out all the neces-
sary procedures on the industry standard JTAG port. Thus, users do not need to learn a new tool or new flows. It
also allows users to implement the feature incrementally.
The block diagram in Figure 17-3 shows the built-in circuitry, Lattice designed into the FPGA product families,
which enable the JTAG port to access the non-JTAG SPI Flash devices. This unique capability also allows the SPI
Flash devices to be live field upgradable.
The four methods shown in Figure 17-3 are listed below.
Golden
1. Power disruption.
2. Communications disruption.
3. Data file corruption.
1. Use ispVM to program the SPI Flash directly during the board development phase.
2. Use ispVME to program the SPI Flash during the board production phase.
3. Use the CPU to access the SPI Flash directly bypassing the LatticeXP2 device.
Option 1:
Primary Pattern in Embedded Flash
Golden Pattern in SPI Flash
SPI
Flash
/S
D
Q
C
CCSPIN
SISPI
SOSPI
CCLK
INITN
PROGRAMN
XP2
Flash
DONE
CFGO
CFG1
17-2
Option 2:
Primary Pattern in SPI Flash
Golden Pattern in Embedded Flash
SPI
Flash
/S
D
Q
C
LatticeXP2 Dual Boot Feature
CCSPIN
SISPI
SOSPI
CCLK
INITN
PROGRAMN
XP2
Flash
Flash
DONE
CFGO
CFG1
Golden