LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 136

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 9-10. Clock Injection Delay Removal Application
PLL Clock Phase Adjustment
In this mode the PLL is used to create fixed phase relationships in 22.5° increments. Creating fixed phase relation-
ships is useful for forward clock interfaces where a specific relationship between clock and data is required.
The fixed phase relationship can be used between CLKI and CLKOS or between CLKOP and CLKOS.
Figure 9-11. CLKOS Phase Adjustment from CLKOP
IPexpress Output
There are two IPexpress outputs that are important for use in the design. The first is the <module_name>.[v|vhd]
file. This is the user-named module that was generated by the tool to be used in both synthesis and simulation
flows. The second is a template file, <module_name>_tmpl.[v|vhd]. This file contains a sample instantiation of the
module. This file is provided for the user to copy/paste the instance and is not intended to be used in the synthesis
or simulation flows directly.
For the PLL, IPexpress sets attributes in the HDL module that are specific to the data rate selected. Although these
attributes can be easily changed, they should only be modified by re-running the GUI so that the performance of
the PLL is maintained. After the map stage in the design flow, FREQUENCY preferences will be included in the
preference file to automatically constrain the clocks produced from the PLL.
CLKI
CLKFB
CLKI
CLKOP
CLKOS with 90°
Phase Shift
CLKI
CLKFB
CLKI
Clock at
Clock Tree
without PLL
CLKOP/CLKOS
at Clock Tree
with PLL
PLL
PLL
Clock Injection Delay
9-14
CLKOP
CLKOP
CLKOS
Clock Tree
LatticeXP2 sysCLOCK PLL
Design and Usage Guide