LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 298

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Slave SPI Mode Operation
The Slave SPI Mode interface to the TAG memory supports both SPI Bus Mode 0 and Mode 3 operations. In SPI
Bus Mode 0 the CLK pin is normally low when the SPI master is in standby and data is not being transmitted. In
SPI Bus Mode 3 the CLK pin is normally high during this condition. In both cases the data at the SISPI pin is sam-
pled on the rising edge of CCLK and the data output on the SOSPI pin is clocked on the falling edge of CCLK.
For more information on using the TAG memory please see TN1137,
User Flash
The User Flash is designed as a non-volatile memory location to back up the data stored in the EBR RAM blocks.
This gives the user a reliable method to save the contents of the RAM memory for later use.
The amount of User Flash for LatticeXP2 devices is directly tied to the number of EBR blocks in the device and it
scales with density. The User Flash is organized physically as either 1- or 2- separate User Flash Modules. How-
ever, all User Flash Modules are logically treated as one unified block.
Table 14-11. User Flash Organization
The EBR blocks act as the primary interface for the User Flash. Users do not have direct access to the User Flash.
The contents of the EBR can be saved into the User Flash via a store-to-flash control signal. The EBR contents
must be saved into the User Flash when required. Two signals, UFMFAIL and UFMBUSYN are provided for keep-
ing track of the status of the store-to-flash command. If the UFMFAIL signal is low and the UFMBUSYN signal is
high then the EBR contents were successfully stored in the Flash memory.
The User Flash memory has the following constraints upon its usage.
• The Store-to-Flash operation has impact only on the EBR RAM (Single-Port, True Dual-Port, Pseudo Dual-Port)
• During the Store-to-Flash operation, the EBR blocks are unavailable for user operation and the Flash is unavail-
• No selective EBR storing is supported. A Store-to-Flash operation will store the contents of all EBR blocks.
• Due to silicon limitations the user cannot use Store-to-Flash operation if the SED is operating in an Always mode.
• UFM mode cannot concurrently be used with Transparent/Background mode (Flash or SRAM). The SSPI config-
Table 14-12. Differences Between User Flash and Shadow Flash (EBR) Behavior
For more information, please see TN1137,
configurations.
able for configuration operation.
uration and verify operations (which are essentially Transparent Mode operations) are initiated by the user and
the user needs to ensure that the UFM operation is not requested at the same time.
Physical UFM blocks
Logical UFM blocks
Read/write access speed
Access nature
Data access
Data organization
Data granularity
Block Type
Parameter
XP2-5K
1
1
Sequential
Slow
Limited (refer to Sec13.3)
Sequential, one bit at a time
Whole UFM block
LatticeXP2 Memory Usage
XP2-8K
User Flash
1
1
14-16
XP2-17K
LatticeXP2 sysCONFIG Usage Guide
LatticeXP2 Memory Usage
2
1
Guide.
Fast
Random
Infinite or unlimited
Flexible, variable data width
One EBR block
Shadow Flash (EBR)
XP2-30K
2
1
Guide.
XP2-40K
2
1