LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 285

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
sysCONFIG Pins
Following is a description of the sysCONFIG pins for the LatticeXP2 device. These pins are used to control or mon-
itor the configuration process. These pins are used for non-JTAG programming sequences only. The JTAG pins will
be explained later in the ispJTAG Pins section of this document.
CFG[1:0]
The Configuration Mode pin CFG0 is a dedicated input with a weak pull-up. The CFG1 pin is a dual-purpose input
pin with a weak pull-up. The CFG pins are used to select the configuration mode for the LatticeXP2, i.e. what type
of device the LatticeXP2 will configure from. At Power-On-Reset (POR), or when the PROGRAMN pin is driven low,
the device will enter the configuration mode selected by the CFG[1:0] pins.
Table 14-2. LatticeXP2 Configuration Modes
When the CFG0 pin is high, the device will configure itself by reading the data stored in on-chip Flash; this is
referred to as SDM, or Self Download Mode. See the Self-Download section of this document for more information
regarding SDM. If the CFG0 pin is low then the device will read the CFG1 pin to determine which mode to enter.
When CFG1 is low the device will first attempt to configure the SRAM using Master SPI mode with the external SPI
Flash port. If this fails then the device will configure itself from the on-chip Flash if a configuration file is stored
there. When CFG1 is high the device will first attempt to configure the SRAM using on-chip Flash. If a configuration
file is not stored there then the device will configure itself using Master SPI mode with the external SPI Flash port.
Dual-Purpose sysCONFIG Pins
The following is a list of the dual-purpose sysCONFIG pins. These pins are available as general purpose I/O after
configuration. If a dual-purpose pin is to be used both for configuration and as a general purpose I/O the user must
adhere to the following:
• The I/O type must remain the same. In other words, if the pin is a 3.3V CMOS pin (LVCMOS33) during configura-
• The Persistent option must be set to OFF. The Persistent option will be set to OFF by the software unless the
• The user is responsible for insuring that no internal or external logic will interfere with device configuration.
After configuration these pins, if not used as GPIO, are tri-stated and weakly pulled up.
Table 14-1. Configuration Pins for the LatticeXP2 Device (Continued)
TMS
1. Weak pull-ups consist of a current source of 30uA to 150uA. The pull-up for CFG tracks V
2. This pin becomes a dedicated programming pin when the CFG0 pin is low.
tion it must remain a 3.3V CMOS pin as a GPIO.
user sets the SLAVE_SPI_PORT to ENABLE using the Design Planner in ispLEVER. This option is shown in the
Global tab of the Design Planner Speadsheet view.
above V
Pin Name
CC
is considered a “high.” The pull-ups for TDI and TMS track V
Input, weak pull-up
SPI Flash Boot
Dual-Boot Mode
Self Download Mode (SDM)
Configuration Mode
I/O Type
14-3
CCJ
; all other pull-ups track the V
CFG[1]
X
0
1
LatticeXP2 sysCONFIG Usage Guide
1
CFG[0]
CC
0
0
1
(core). This means that any voltage level
Pin Type
JTAG
CCIO
for that pin.
Mode Used