LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 324

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Dual Boot Mode
The LatticeXP2 Dual Boot sysCONFIG™ mode is selected using CFG pin settings. ists the sysCONFIG modes
supported by the LatticeXP2 device family. Figure 17-1 illustrates the SPI Flash hardware connections.
Table 17-2. LatticeXP2 sysCONFIG Modes
Figure 17-5. LatticeXP2 Hardware Connections to SPI Flash
Internal logic is used to detect a configuration failure from the primary source and provides the ability to reattempt
configuration from the secondary source. This sequence is used when the LatticeXP2 is set to dual boot mode and
configuration is initiated.
Configuration initiates in dual boot mode when any of the following events occur:
• The device is powered-up with all supplies reaching their required minimum values.
• The PROGRAMN pin is toggled.
• The REFRESH command is issued via the ispJTAG™ port.
Should configuration from both primary and golden images in dual boot mode fail, the INITN pin will be driven low
and the configuration process will halt.
Lattice strongly recommends using the embedded Flash as the first (Primary) boot to take full advantage of the fea-
tures only embedded Flash can offer, for example fast instant-on time, standard or advance security, and TransFR.
The dual boot flow described in this document focus only on setting CFG[0:1] to [01], respectively, to select the
embedded Flash as the first boot.
This flow is triggered either by power cycling or toggle the PROGRAMN pin.
A. When the dual boot mode is selected by setting the CFG0 to low (0), the device checks the CFG1 pin first to
decide the source of the first boot. It the CFG1 pin is high (1), the device will check the Flash done fuse immedi-
ately.
1. Done Fuse Programmed
CFG0

If the Done fuse is programmed, then the embedded Flash must have been programmed with a valid pat-
0
0
1
CFG1
X
0
1
Self Download Mode (SDM)
Configuration Mode
SPI Serial Flash
Primary or
Dual Boot
Dual Boot
Golden
Image
17-6
Primary Boot Source
External SPI Flash
Internal Flash
Internal Flash
CCSPIN
SISPI
SOSPI
CCLK
Internal Flash Memory
LatticeXP2
LatticeXP2 Dual Boot Feature
Secondary Boot Source
External SPI Flash
Internal Flash
None