LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 175

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Data_X data inputs do not get written as the FIFO is full (the Full flag is high).
Now let us look at the waveforms when the contents of the FIFO are read out. Figure 10-23 shows the start of the
read cycle. RdEn goes high and the data read starts. The Full and Almost Full flags are de-asserted, as shown.
Figure 10-23. FIFO without Output Registers, Start of Data Read Cycle
Similarly, as the data is read out and FIFO is emptied, the Almost Empty and Empty flags are asserted.
Figure 10-24. FIFO without Output Registers, End of Data Read Cycle
Figures 10-21 to 10-24 show the behavior of non-pipelined FIFO or FIFO without output registers. When we pipe-
line the registers, the output data is delayed by one clock cycle. There is also the extra option for Output registers to
be enabled by the RdEn signal.
Almost Full
Almost Full
Almost
Almost
Empty
Empty
Empty
Empty
Reset
Clock
WrEn
RdEn
Reset
Clock
WrEn
RdEn
Data
Data
Full
Full
Q
Q
Data_N-4
Invalid Data
Data_N-3
Data_1
Data_N-2
Data_2
10-25
Invalid Data
Invalid Data
Data_N-1
Data_3
LatticeXP2 Memory Usage Guide
Data_4
Data_N
Data_5