LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 11

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
LatticeXP2 Hardware Checklist
Section III. LatticeXP2 Family Handbook Revision History
Reference Material......................................................................................................................................... 17-14
References..................................................................................................................................................... 17-15
Technical Support Assistance........................................................................................................................ 17-16
Revision History ............................................................................................................................................. 17-16
Introduction ...................................................................................................................................................... 18-1
Power Supply ................................................................................................................................................... 18-1
Configuration.................................................................................................................................................... 18-2
I/O Interface and Critical Pins .......................................................................................................................... 18-3
Checklist........................................................................................................................................................... 18-5
Technical Support Assistance.......................................................................................................................... 18-5
Revision History ............................................................................................................................................... 18-5
Revision History ............................................................................................................................................... 19-1
Part 2: Program the Primary Pattern into LatticeXP2 Embedded Flash ............................................... 17-12
LatticeXP2 Bitstream File Format ......................................................................................................... 17-14
Implement SPI Flash Programming on ispVM System ......................................................................... 17-14
Power Supply Sequencing ...................................................................................................................... 18-1
Power Supply Ramp ............................................................................................................................... 18-2
Power Estimation .................................................................................................................................... 18-2
JTAG Interface ........................................................................................................................................ 18-3
I/O Pin Assignments Around V
DDR/DDR2 Memory Interface Pin Assignments..................................................................................... 18-4
True-LVDS Output Pin Assignments....................................................................................................... 18-4
HSTL and SSTL Pin Assignments .......................................................................................................... 18-4
PCI Clamp Pin Assignment..................................................................................................................... 18-4
Test Output Enable (TOE) ...................................................................................................................... 18-4
CCPLL
...................................................................................................... 18-3
10
LatticeXP2 Family Handbook
Table of Contents