LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 264

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Lattice XP2 sysDSP Usage Guide
Figure 13-5. MAC Mode Advanced Set-up
MULTADDSUB Module
The MULTADDSUB GUI configures multiplier addition/subtraction elements to be packed into the primitives
MULT18X18ADDSUBB or MULT9X9ADDSUBB. The Basic mode, shown in Figure 13-6, consists of an optional
one clock, one clock enable and one reset tied to all registers. Multiple sysDSP Blocks can be spanned to accom-
modate large multiplications. If sysDSP blocks are spanned, additional LUT logic may be required. Select
Area/Speed to determine the LUT implementation. The input data format can be selected as Parallel, Shift or
Dynamic. The Shift format can only be enabled if inputs are less than 18 bits. The Shift format enables a sam-
ple/shift register, which is useful in applications such as the FIR filter. The Advanced mode, shown in Figure 13-7,
provides finer control over the registers. In the advanced mode, users can control each register with independent
clocks, clock enables and resets. MULTADDSUB inputs can be from 2 to 72 bits.
13-5