LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 156

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
LatticeXP2 Memory Usage Guide
The various memory modules, both EBR and distributed, are discussed in detail in this document.
Memory Modules
ECC is supported in most memories. If you choose to use ECC, you will have a 2-bit error signal.
• When Error[1:0]=00, there is no error.
• When Error[0]=1, it indicates that there was a 1 bit error which was fixed.
• When Error[1]=1, it indicates that there was a 2-bit error which cannot be corrected.
Single Port RAM (RAM_DQ) – EBR Based
The EBR blocks in LatticeXP2 devices can be configured as Single Port RAM or RAM_DQ. IPexpress allows users
to generate the Verilog-HDL or VHDL along EDIF netlist for the memory size as per design requirements.
IPexpress generates the memory module as shown in Figure 10-5.
Figure 10-5. Single Port Memory Module Generated by IPexpress
Clock
ClockEn
RAM_DQ
Reset
Q
EBR-based Single Port
WE
Memory
Address
Data
Since the device has a number of EBR blocks, the generated module makes use of these EBR blocks, or primi-
tives, and cascades them to create the memory sizes specified by the user in the IPexpress GUI. For memory sizes
smaller than an EBR block, the module will be created in one EBR block. For memory sizes larger than one EBR
block, multiple EBR blocks can be cascaded in depth or width (as required to create these sizes).
In Single Port RAM mode, the input data and address for the ports are registered at the input of the memory array.
The output data of the memory is optionally registered at the output.
The various ports and their definitions for the Single Port Memory are listed in Table 10-2. The table lists the corre-
sponding ports for the module generated by IPexpress and for the EBR RAM_DQ primitive.
10-6