LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 292

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
LatticeXP2 sysCONFIG Usage Guide
The CSSPISN enables and disables the SPI interface operation. When CSSPISN is high the SPI interface is dese-
lected and the SOSPI pin is at high impedance. When CSSPISN is brought low the SPI interface is selected, com-
mands can be written into and data read from the LatticeXP2. After power up the CSSPISN must transition from
high to low before a new command can be accepted.
The Slave SPI mode can also be used to access on-chip Flash. The CSSPISN pin must be held low to write to on-
chip Flash; data is input from SISPI. The Slave SPI mode can also be used for readback of both Flash and SRAM.
By driving the CSSPISN low, the device will input the readback instructions on the SISPI pin and the data will be
written out on the SOSPI pin; a bit in the read command will determine if the read is directed to Flash or SRAM. In
order to support readback while the device is in user mode (the DONE pin is high), the SLAVE_SPI_PORT prefer-
ence must be set to ENABLE using the Design Planner.
Master SPI Mode
In Master SPI mode the LatticeXP2 will drive CCLK out to the Slave SPI Flash device that will provide the bit-
stream. The Master device will write commands out on SISPI at the rising edge of CCLK and will accept data on
SOSPI at the falling edge of CCLK. The Master Serial device starts driving CCLK at the beginning of the configura-
tion and continues to drive CCLK until the external DONE pin is driven high and an additional 100 to 500 clock
cycles have been generated. The CCLK frequency on power up defaults to 2.5 MHz. The master clock frequency
default remains unless a new clock frequency is loaded from the bitstream.
Self Download Mode
Self Download Mode (SDM) allows the FPGA to configure itself without using any external devices, and because
the bitstream is not exposed this is also a very secure configuration mode. The user may access on-chip Flash
using ispJTAG or the slave SPI port pins.
JTAG may access the on-chip Flash any time the device is powered up, without disturbing device operation. JTAG
may also read and write the configuration SRAM. If access to the on-chip Flash and SRAM is limited to JTAG then
SLAVE_SPI_PORT can be set to DISABLE, freeing the dual-purpose pins for use as general purpose I/O.
ispJTAG Mode
The LatticeXP2 device can be configured through the ispJTAG port. The ispJTAG port is always on and available,
regardless of the configuration mode selected. The SLAVE_SPI_PORT can be set to DISABLE in the Lattice isp-
LEVER design software to tell the place and route tools that the JTAG port will be used exclusively, i.e. the SPI port
will not be used. Setting the SLAVE_SPI_PORT to DISABLE allows software to use all of the dual-purpose pins as
general purpose I/Os.
ISC 1532
Configuration through the ispJTAG port conforms to the IEEE 1532 Standard. The Boundary Scan cells take con-
trol of the I/Os during any 1532 mode instruction. The Boundary Scan cells can be set to a pre-determined value
whenever using the JTAG 1532 mode. Because of this the dedicated pins, such as DONE, cannot be relied upon
for valid configuration status.
Transparent Readback
The ispJTAG Transparent Readback mode allows the user to read the content of the device SRAM or Flash while
the device remains in a functional state. Care must be exercised when reading EBR and distributed RAM, as it is
possible to cause conflicts with accesses from the user design (causing possible data corruption).
The I/O and non-JTAG configuration pins remain active during a Transparent Readback. The device enters the
Transparent Readback mode through a JTAG instruction.
Boundary Scan and BSDL Files
BSDL files for this device can be found on the Lattice website at www.latticesemi.com. The boundary scan ring
covers all of the I/O pins, as well as the dedicated and dual-purpose sysCONFIG pins.
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