LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 102

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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April 2011
Revision History
September 2007
February 2008
April 2008
May 2007
Date
Version
01.1
01.2
01.3
01.4
Ordering Information
Pinout Information
Pinout Information
DC and Switching
DC and Switching
DC and Switching
Characteristics
Characteristics
Characteristics
Architecture
Section
—
Initial release.
Added JTAG Port Timing Waveforms diagram.
Updated sysCLOCK PLL Timing table.
Added Thermal Management text section.
Added LVCMOS33D to Supported Output Standards table.
Clarified: “This Flash can be programmed through either the JTAG or
Slave SPI ports of the device. The SRAM configuration space can also
be infinitely reconfigured through the JTAG and Master SPI ports.”
Added External Slave SPI Port to Serial TAG Memory section. Updated
Serial TAG Memory diagram.
Updated Flash Programming Specifications table.
Added “8W” specification to Hot Socketing Specifications table.
Updated Timing Tables
Clarifications for IIH in DC Electrical Characteristics table.
Added LVCMOS33D section
Updated DOA and DOA (Regs) to EBR Timing diagrams.
Removed Master Clock Frequency and Duty Cycle sections from the
LatticeXP2 sysCONFIG Port Timing Specifications table. These are
listed on the On-chip Oscillator and Configuration Master Clock Charac-
teristics table.
Changed CSSPIN to CSSPISN in description of t
parameters. Removed t
Clarified On-chip Oscillator documentation
Added Switching Test Conditions
Added “True LVDS Pairs Bonding Out per Bank,” “DDR Banks Bonding
Out per I/O Bank,” and “PCI capable I/Os Bonding Out per Bank” to Pin
Information Summary in place of previous blank table “PCI and DDR
Capabilities of the Device-Package Combinations”
Removed pinout listing. This information is available on the LatticeXP2
product web pages
Added XP2-17 “8W” and all other family OPNs.
Updated Absolute Maximum Ratings footnotes.
Updated Recommended Operating Conditions Table footnotes.
Updated Supply Current (Standby) Table
Updated Initialization Supply Current Table
Updated Programming and Erase Flash Supply Current Table
Updated Register to Register Performance Table
Updated LatticeXP2 External Switching Characteristics Table
Updated LatticeXP2 Internal Switching Characteristics Table
Updated sysCLOCK PLL Timing Table
LatticeXP2 Family Data Sheet
7-1
SOE
Change Summary
parameter.
Revision History
SCS
Data Sheet DS1009
, t
SCSS
, and t
SCSH