LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 286

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
LatticeXP2 sysCONFIG Usage Guide
CFG1
The CFG1 pin is a dual-purpose input with a weak pull-up. Its function is described in the section above. When the
CFG0 pin is high, the CFG1 pin is not used for configuration and becomes a general purpose I/O pin available to
the user.
PROGRAMN
The PROGRAMN pin is a dual-purpose input with a weak pull-up. This pin is used to initiate a non-JTAG SRAM
configuration sequence. A high to low signal applied to PROGRAMN sets the device into configuration mode. The
PROGRAMN pin can be used to trigger configuration at any time. If the device is using JTAG then PROGRAMN will
be ignored until the device is released from JTAG mode.
The PROGRAMN pin is only available if the CFG0 pin is set to 0 (not in SDM mode). When the CFG0 pin is set to
1 then PROGRAMN becomes a general purpose I/O pin available to the user.
When the CFG0 pin is set to 0, the PROGRAMN pin becomes a dedicated programming pin.
INITN
The INITN pin is a dual-purpose bi-directional open drain pin with a weak pull-up. INITN is capable of driving a low
pulse out as well as detecting a low pulse driven in.
When using either the SPI Flash boot or Embedded Flash Boot mode to configure the SRAM, INITN going low indi-
cates that the SRAM is being initialized; INITN going high indicates that the FPGA is ready to accept configuration
data. To delay configuration the INITN pin can be held low externally. The device will not enter configuration mode
as long as the INITN pin is held low. After configuration has started INITN is used to indicate a bitstream error. The
INITN pin will be driven low if the calculated CRC and the configuration data CRC do not match; DONE will then
remain low and the LatticeXP2 will not wake up.
When using SDM, configuration from on-chip Flash INITN is not used or monitored.
When programming on-chip Flash the INITN pin is not used. During Flash Direct programming an error will prevent
the FPGA from configuring from the Flash, during Flash Background programming an error will not affect the con-
figuration already running in SRAM.
The INITN pin is only available if the CFG0 pin is set to 0 (not in SDM mode). When the CFG0 pin is set to 1 then
INITN becomes a general purpose I/O pin available to the user.
When the CFG0 pin is set to 0, the INITN pin becomes a dedicated programming pin.
DONE
The DONE pin is a dual-purpose bi-directional open drain with a weak pull-up (default), or an actively driven pin.
DONE will be driven low when the device is in configuration mode and the internal DONE bit is not programmed.
When the INITN and PROGRAMN pins go high, and the internal DONE bit is programmed, the DONE pin will be
released (or driven high, if it is an actively driven pin). The DONE pin can be held low externally and, depending on
the wake-up sequence selected, the device will not become functional until the DONE pin is externally brought
high.
Reading the DONE bit is a good way for an external device to tell if the FPGA is configured.
When using JTAG to configure SRAM the DONE pin is driven by the boundary scan cell, so the state of the DONE
pin has no meaning until configuration is completed.
The DONE pin is only available if the CFG0 pin is set to 0 (not in SDM mode). When the CFG0 pin is set to 1 then
DONE becomes a general purpose I/O pin available to the user.
When the CFG0 pin is set to 0, the DONE pin becomes a dedicated programming pin.
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