LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 233

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 11-34. IDDRX2B Waveform
ODDRXC
This is the DDR output module. This primitive will input two data streams and mux them together to generate a sin-
gle stream of data going to the sysIO™ buffer. The CLK to this module can be connected to the edge clock or to the
FPGA clock. This primitive is also used for when DDR function is required for the tristate signal.
Figure 11-35 shows the primitive symbol for the ODDRXC mode.
Figure 11-35. ODDRXC Symbol
Table 11-9 lists the port names and descriptions for the ODDRXC primitive.
DDR DATA at IDDRX2B
ECLK (shifted 90 deg)
DDR DATA at I/O
CLK at I/O
SCLK
QB1
QA1
QB0
QB1
D/E
F/G
C
A
B
P0
P0
XX
XX
XX
P0
N0
N0
P0
CLK
DA
DB
RST
N0
P1
P1
XX
P0/N0
ODDRXC
11-29
P1
N1
N1
XX
XX
XX
XX
N1
P1
P2
P2
Q
LatticeXP2 High-Speed I/O Interface
P1/N1
P0/N0
P2
N2
N2
N2
P2
P3
P3
N0
N1
P0
P1
P2/N2
P1/N1
P3
N3
N3
P3
N3
P4
P4
P3/N3
P2/N2
P4
N4
P4
N4
N2
P2
P3
N3