LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 335

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

March 2011
Introduction
Starting a complex system with a large FPGA hardware design requires that the FPGA designer pay attention to
the critical hardware implementation to increase the chances of success for the hardware. This technical note sys-
tematically steps through these critical hardware implementation items relative to the LatticeXP2™ device.
LatticeXP2 is the third-generation non-volatile FPGA from Lattice with on-chip Flash to store the configuration. The
device family consists of FPGA LUT densities ranging from 5K to 40K. This technical note assumes that the reader
is familiar with the LatticeXP2 device features as described in the
The critical hardware areas covered in this technical note are:
• Power supplies as they related to the LatticeXP2 supply rails and how to connect them to the PCB and the asso-
• Configuration and how to connect the configuration mode selection for proper power up configuration
• Device I/O interface and critical signals
Power Supply
The V
two power supplies, there are V
All power supplies are required for the proper device operation but since V
power-on condition, it is recommended to have one of these supplies be the final power supply to power up the
LatticeXP2 device after all other power supplies are stable. Table 18-1 shows the power supplies and the appropri-
ate voltage levels for each supply.
Table 18-1. Power Supply Description and Voltage Levels
V
V
V
V
V
Power Supply Sequencing
There is no specific power sequencing requirement for the LatticeXP2 device family. If the user's system has the
option to design for power sequencing, a practical sequencing to keep in mind is based on the fact that V
V
the V
sequencing considerations should also consider that common supplies generally are tied together to the same rail.
For example, if there is a 3.3V V
able to tolerate any order of power sequencing without causing any high current leakage paths during power up.
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Supply
CC
CCAUX
CCPLL
CCIO0-7
CCJ
CCAUX
ciated system
CCIO
CC
determine when the core powers up. In order insure proper functional behavior, it is desirable to bring up
and V
, V
Voltage (Typ.)
1.2V to 3.3V
1.2V to 3.3V
CCJ
CCAUX
1.2V
3.3V
3.3V
and V
power supplies determine the LatticeXP2 internal “power good” condition. In addition to the
CCPLL
Core power supply. A typical V
0.7V and 0.9V.
Auxiliary power supply. A 3.3V supply that provides an internal reference to the input buffers. A
typical V
Power supply for PLL.
I/O power supply. There are eight banks of I/Os and each bank has its own supply V
V
JTAG power supply for TAP controller port.
CCIO7
first in any order and bring up V
CCIO
CCIO0-7
.
CCAUX
, it should be tied to the same supply as the 3.3V rail for V
, V
device internal power up and power down trip point is between 2.0V and 2.8V.
CCPLL
and V
CC
CCJ
18-1
device internal power up and power down trip point is between
supplies that power the I/O banks, PLL and JTAG port.
CC
first and V
Description
LatticeXP2 Family Data
LatticeXP2 Hardware
CCAUX
CC
and V
next in a sequential order. Power
CCAUX
Sheet.
Technical Note TN1143
determine the device
CCAUX
Checklist
. LatticeXP2 is
CCIO0
tn1143_01.1
CC
to
and