LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 108

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
V
There are a total of eight V
single-ended output drivers and the ratioed input buffers such as LVTTL, LVCMOS, and PCI. LVTTL, LVCMOS3.3,
LVCMOS2.5 and LVCMOS1.2 also have fixed threshold options allowing them to be placed in any bank. The V
voltage applied to the bank determines the ratioed input standards that can be supported in that bank. It is also
used to power the differential output drivers.
V
In addition to the bank V
that powers the differential and referenced input buffers. V
3.3V to satisfy the common-mode range of the drivers and input buffers.
V
The JTAG pins have a separate V
mines the electrical characteristics of the LVCMOS JTAG pins, both the output high level and the input threshold.
Table 8-3 shows a summary of all the required power supplies.
Table 8-3. Power Supplies
Input Reference Voltage (V
Each bank can support up to two separate V
old for the referenced input buffers. The locations of these V
pins can be used as regular I/Os if the bank does not require a V
V
When interfacing to DDR memory, the V
input from the memory. A voltage divider between V
age that is used by the DQS transition detector circuit. This voltage divider is only present on V
able on V
Lattice technical note number TN1138,
V
this should be connected to 0.9V, and only SSTL18_II signaling is allowed.
Mixed Voltage Support in a Bank
The LatticeXP2 sysIO buffer is connected to three parallel ratioed input buffers. These three parallel buffers are
connected to V
olds for 3.3V (V
a pin-by-pin basis rather than tracking with V
and is independent of the bank V
and 3.3V ratioed input buffers with fixed thresholds, as well as 2.5V ratioed inputs with tracking thresholds.
REF1
CCIO
CCAUX
CCJ
REF1
should be connected to 1.25V. Therefore, only SSTL25_II signaling is allowed. For DDR2 memory interfaces
(1.2V/1.5V/1.8V/2.5V/3.3V)
(1.2V/1.5V/1.8V/2.5V/3.3V)
for DDR Memory Interface
REF2
(3.3V)
Power Supply
V
V
V
V
1. Refer to the
2. If V
CC
CCIO
CCAUX
CCJ
. For more information on the DQS transition detect logic and its implementation, please refer to
2
CCIO
CCIO
CCAUX
2
or V
, V
) and 1.2V (V
CCAUX
LatticeXP2 Family Data Sheet
CCJ
CCIO
Core Power Supply
Power Supply for the I/O Banks
Auxiliary Power Supply
Power Supply for JTAG Pins
is set to 3.3V, they MUST be connected to the same power supply as VCCAUX.
CCIO
and V
supplies, devices have a V
supplies, V
CCIO
REF1,
CCJ
CC
CC
) inputs. This allows the input threshold for ratioed buffers to be assigned on
, giving support for thresholds that track with V
power supply that is independent of the bank V
voltage. For example, if the bank V
LatticeXP2 High Speed I/O
V
REF1
CCIO0
REF2
Description
CCIO
REF
input must be used as the reference voltage for the DQS and DQ
for recommended min. and max. values.
)
- V
. This option is available for all 1.2V, 2.5V and 3.3V ratioed inputs
input voltages, V
CCIO7
REF1
8-4
CC
. Each bank has a separate V
and GND is used to generate an on-chip reference volt-
CCAUX
core logic power supply and a V
REF
REF
is used to supply I/O reference voltage requiring
pins are pre-determined within the bank. These
REF1
voltage.
Interface. For DDR1 memory interfaces, the
and V
1.2V
1.2V/1.5V/1.8V/2.5V/3.3V
3.3V
1.2V/1.5V/1.8V/2.5V/3.3V
CCIO
LatticeXP2 sysIO Usage Guide
REF2
is 1.8V, it is possible to have 1.2V
, that are used to set the thresh-
CCIO
Value
CCIO
CCIO
as well as fixed thresh-
1
supply that powers the
CCAUX
supplies. V
REF1
auxiliary supply
it is not avail-
CCJ
deter-
CCIO