LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 318

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Revision History
September 2009
February 2007
February 2008
January 2008
January 2008
January 2009
January 2009
August 2008
March 2008
April 2008
July 2008
Date
Version
01.0
01.1
01.2
01.3
01.4
01.5
01.6
01.7
01.8
01.9
02.0
Initial release.
Updated code in the following sections: Basic SED VHDL Example,
One Shot SED in VHDL, Basic SED Verilog Example, One Shot SED in
Verilog.
Updated OSC_DIV text section.
Updated SED Flow text section.
Updated Timing Diagram.
Updated SEDCLKIN and OSC_DIV text sections and SEDENABLE
table.
Corrected “SEDFRCERR” to read “SEDFRCERRN”.
Added footnote to SED Flow timing diagram.
Updated SEDCLKIN and OSC_DIV text sections.
Updated SED Run Time text section and SED Run Time table.
Updated SED Flow text section. Added Example Schematic diagram.
Updated Basic SED Verilog Example code.
Updated One-Shot SED in Verilog code.
Updated Basic SED VHDL Example code.
Updated One-Shot SED in VHDL code.
16-10
Change Summary
Detection Usage Guide
LatticeXP2 Soft Error