LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 143
![FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd](/photos/16/14/161486/bga256_sml.jpg)
LFXP2-5E-5FTN256I
Manufacturer Part Number
LFXP2-5E-5FTN256I
Description
FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-5E-5FTN256I
Number Of Macrocells
5000
Number Of Programmable I/os
172
Data Ram Size
169984
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FTBGA-256
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
169984
Number Of I /o
172
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Lattice Semiconductor
Figure 9-20. Timing Diagrams by DCS MODE (Cont.)
DCS Usage with VHDL - Example
COMPONENT DCS
-- synthesis translate_off
-- synthesis translate_on
END COMPONENT;
begin
DCSInst0: DCS
-- synthesis translate_off
attribute DCSMODE : string;
attribute DCSMODE of DCSinst0 : label is “POS”;
DCSOUT
DCSOUT
SEL
SEL
CLK1
CLK1
GENERIC
PORT
GENERIC MAP (
- Switch low @CLK1 falling edge.
- If SEL is low, output stays low at on
- Switch high @CLK1 rising edge.
- If SEL is low, output stays low high
CLK1 rising edge. SEL must not
change during setup prior to rising clock.
on CLK1 falling edge.
DCS MODE = HIGH_HIGH
DCS MODE = HIGH_LOW
(
DCSMODE : string :=
;
(
“POS”
9-21
DCSOUT
DCSOUT
SEL
SEL
CLK0
CLK0
- Switch low @CLK0 falling edge.
- If SEL is high, output stays low at
- Switch high @ CLK0 rising edge.
- If SEL is high, output stays high on
on CLK0 rising edge.
CLK0 falling edge.
DCS MODE = LOW_HIGH
DCS MODE = LOW_LOW
LatticeXP2 sysCLOCK PLL
Design and Usage Guide
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