LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 194

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
face is selected and commands can be written into and data read from the device. After power up, CS must transit
from high to low before a new command can be accepted.
SPI Operations
SPI Modes
The SPI interface is accessible through the SPI-compatible bus consisting of four signals: Serial Clock (CLK), Chip
Select (CS), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus operation Modes 0 (0,0) and 3 (1,1)
are supported. The primary difference between Mode 0 and Mode 3 concerns the normal state of the CLK pin
when the SPI master is in standby and data is not being transferred to the device’s SPI interface. For Mode 0 the
CLK is normally low and for Mode 3 the CLK signal is normally high. In either case, data input on the SI pin is sam-
pled only during the rising edge. Data output on the SO pin is clocked out only on the falling edge of CLK.
Status Register
The SPI interface can access the 1-bit status register required to support TAG Memory Flash programming.
The programming complete status register: This is the single bit status register for pooling. If the programming or
erase operation is complete, then the status bit is set to 1, otherwise it is set to 0 for more programming or erase
time.
Commands
Table 10-21. Commands
READ_ID (98h)
The READ_ID command captures the IEEE 1149.1 JTAG IDCODE out of the device on the SO pin. This command
is commonly used to verify whether communication is established with the SPI bus. After the 8-bit READ_ID com-
mand is received, the device ignores the data presented at the Serial Data Input (SI) pin. The Serial Output (SO)
pin is enabled on the falling edge of clock 31 to drive out the first bit of the IDCODE. After 32 bits of the IDCODE
are shifted out, additional clocking will cause dummy data to be shifted out on SO.
READ_ID
WRITE_EN
WRITE_DIS
ERASE_TAG
PROGRAM_TAG
READ_TAG
STATUS
Notes:
1. Data bytes are shifted with most significant bit first. Byte field with data in parenthesis ( ) indicate data being read from the SO pin.
2. Byte 2-4 are dummy clocks to provide extra timing for the device to execute the command. The data presented at the SI pin during these
3. The READ_ID command reads out the 32 bits JTAG IDCODE of the device. The first bit shifted out on SO pin is thus bit 0 of the JTAG
4. The PROGRAM_TAG command supports page programming only. The programming data shift into the TAG Memory must be exactly the
5. The STATUS command read from the single bit status register. When read from the register, only the first bit is valid, the other bits are dum-
dummy clocks can be any value and do not have to be 0x00 as shown.
IDCODE and the last bit is bit 31 of the IDCODE.
same size as the one page of the TAG Memory. Under shifting or over shifting will cause erroneous data programmed into the TAG Mem-
ory. The Last Byte shown on the n-Byte column indicates the last byte of the data must be shifted into the device before driving the Chip
Select to high to start the programming action.
mies and should be ignored.
Command Name
(Opcode)
Byte 1
0xAC
0x98
0x78
0x0E
0x8E
0x4E
0x4A
Byte 2
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Byte 3
0x00
0x00
0x00
0x00
0x00
0x00
0x00
10-44
Byte 4
0x00
0x00
0x00
0x00
0x00
0x00
0x00
LatticeXP2 Memory Usage Guide
(b1xxxxxxx
b0xxxxxxx)
(D0-D7)
(D7-D0)
Byte 5
D7-D0
or
(Next Byte)
Next Byte
(D8-D15)
Byte 6
(D24-D31)
(Continue)
Last Byte
n-Byte