LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 4

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Pinout Information
Ordering Information
Supplemental Information
LatticeXP2 Family Data Sheet Revision History
Section II. LatticeXP2 Family Technical Notes
LatticeXP2 sysIO Usage Guide
Signal Descriptions ............................................................................................................................................ 4-1
PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin .................................................... 4-3
Pin Information Summary................................................................................................................................... 4-4
Logic Signal Connections................................................................................................................................... 4-5
Thermal Management ........................................................................................................................................ 4-5
For Further Information ...................................................................................................................................... 4-5
Part Number Description.................................................................................................................................... 5-1
Ordering Information .......................................................................................................................................... 5-1
For Further Information ...................................................................................................................................... 6-1
Revision History ................................................................................................................................................. 7-1
Introduction ........................................................................................................................................................ 8-1
sysIO Buffer Overview ....................................................................................................................................... 8-1
Supported sysIO Standards ............................................................................................................................... 8-1
sysIO Banking Scheme...................................................................................................................................... 8-3
LVCMOS Buffer Configurations ......................................................................................................................... 8-6
Software sysIO Attributes................................................................................................................................... 8-7
Design Considerations and Usage................................................................................................................... 8-10
Lead-Free Packaging................................................................................................................................ 5-2
Conventional Packaging ........................................................................................................................... 5-5
SPI Flash Interface.................................................................................................................................... 8-3
JTAG Interface .......................................................................................................................................... 8-3
V
V
V
Input Reference Voltage (V
V
Mixed Voltage Support in a Bank.............................................................................................................. 8-4
sysIO Standards Supported by Bank ........................................................................................................ 8-5
Bus Maintenance Circuit ........................................................................................................................... 8-6
Programmable Drive ................................................................................................................................. 8-6
Programmable Slew Rate ......................................................................................................................... 8-6
Open-Drain Control ................................................................................................................................... 8-6
Differential SSTL and HSTL support......................................................................................................... 8-6
PCI Support with Programmable PCICLAMP ........................................................................................... 8-7
Programmable Input Delay ....................................................................................................................... 8-7
IO_TYPE ................................................................................................................................................... 8-7
OPENDRAIN............................................................................................................................................. 8-8
DRIVE ....................................................................................................................................................... 8-8
PULLMODE .............................................................................................................................................. 8-9
PCICLAMP................................................................................................................................................ 8-9
SLEWRATE .............................................................................................................................................. 8-9
FIXEDDELAY.......................................................................................................................................... 8-10
INBUF ..................................................................................................................................................... 8-10
DIN/DOUT............................................................................................................................................... 8-10
LOC......................................................................................................................................................... 8-10
Banking Rules ......................................................................................................................................... 8-10
Differential I/O Rules ............................................................................................................................... 8-10
CCIO
CCAUX
CCJ
REF1
(1.2V/1.5V/1.8V/2.5V/3.3V).............................................................................................................. 8-4
(1.2V/1.5V/1.8V/2.5V/3.3V) ............................................................................................................ 8-4
for DDR Memory Interface ............................................................................................................. 8-4
(3.3V) ........................................................................................................................................... 8-4
REF1,
V
REF2
)................................................................................................... 8-4
3
LatticeXP2 Family Handbook
Table of Contents