LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 109

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Prior to device configuration, the ratioed input thresholds always tracks the bank V
effect after configuration. Output standards within a bank are always set by V
dards that can be mixed in the same bank.
Table 8-4. Mixed Voltage Support
sysIO Standards Supported by Bank
Table 8-5. I/O Standards Supported by Bank
I/O Buffers
Output Standards
Supported
Inputs
Clock Inputs
PCI Support
LVDS Output Buffers
1. These differential standards are implemented by using a complementary LVCMOS driver with external resistor pack.
2. Available only on 50% of the I/Os in the bank.
V
1.2V
1.5V
1.8V
2.5V
3.3V
CCIO
Description
1.2V
Yes
Yes
Yes
Yes
Yes
Single-ended
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18 Class I, II
SSTL25 Class I, II
SSTL33 Class I, II
HSTL15 Class I
HSTL18_I, II
SSTL18D Class I, II
SSTL25D Class I, II
SSTL33D Class I, II
HSTL15D Class I
HSTL18D Class I, II
MLVDS
LVDS25E
LVPECL
BLVDS
RSDS
All Single-ended,
Differential
All Single-ended,
Differential
PCI33 with clamp
1.5V
Yes
Input sysIO Standards
Banks 0-1
1
1
Top Side
1
1
1.8V
Yes
Single-ended and
Differential
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18 Class I, II
SSTL25 Class I, II
SSTL33 Class I, II
HSTL15 Class I
HSTL18 Class I, II
SSTL18D Class I, II
SSTL25D Class I, II
SSTL33D Class I, II
HSTL15D Class I
HSTL18D Class I, II
MLVDS
LVDS
LVDS25E
LVPECL
BLVDS
RSDS
All Single-ended,
Differential
All Single-ended,
Differential
PCI33 without clamp
LVDS (3.5mA) Buffers
2.5V
Yes
Yes
Yes
Yes
Yes
Right Side
1
Banks 2-3
1
1
1
3.3V
Yes
Yes
Yes
Yes
Yes
8-5
2
1.2V
Single-ended
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18 Class I, II
SSTL2 Class I, II
SSTL3 Class I, II
HSTL15 Class I
HSTL18 Class I, II
SSTL18D Class I, II
SSTL25D Class I, II,
SSTL33D Class I, II
HSTL15D Class I
HSTL18D Class I, II
MLVDS
LVDS25E
LVPECL
BLVDS
RSDS
All Single-ended,
Differential
All Single-ended,
Differential
PCI33 with clamp
Yes
Bottom Side
1
Banks 4-5
1
1
1
LatticeXP2 sysIO Usage Guide
1.5V
Yes
CCIO
Output sysIO Standards
. Table 8-4 shows the sysIO stan-
CCIO
1.8V
Yes
Single-ended and
Differential
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18 Class I
SSTL2 Class I, II
SSTL3 Class I, II
HSTL15 Class I, III
HSTL18 Class I, II, III
SSTL18D Class I,
SSTL25D Class I, II,
SSTL33D_I, II
HSTL15D Class I
HSTL18D Class I, II
MLVDS
LVDS
LVDS25E
LVPECL
BLVDS
RSDS
All Single-ended,
Differential
All Single-ended,
Differential
PCI33 without clamp
LVDS (3.5mA) Buffers
. This option only takes
1
1
1
Banks 6-7
1
Left Side
2.5V
Yes
3.3V
2
Yes