LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 234

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 11-9. ODDRXC Port Names
Figure 11-36 shows the Output Register Block of the LatticeXP2 device configured in ODDRXC mode.
Figure 11-36. Output Register Block in ODDRC Mode
Figure 11-37 shows the timing waveform when using the ODDRXC module.
Figure 11-37. ODDRXC Waveform
ODDRX2B
This DDR output module can be used when a gearbox function is required. This primitive inputs four data streams
and muxes them together to generate a single stream of data going to the sysIO buffer.
Latch C0
Reg B0
Reg A0
ECLK
DB
DA
Q
DA
DB
CLK
RST
Q
ECLK
DA
Port Name
DB
XX
XX
XX
XX
XX
XX
P0
N0
I/O
O
I
I
I
I
Data at the negative edge of the clock
Data at the positive edge of the clock
This clock can be connected to the edge clock or to the FPGA clock
Reset signal
DDR data output
P0
N0
P0
P1
N1
A0
B0
N0
N0
ODDRXC
11-30
N1
P1
P1
P2
N2
C0
N1
Definition
N1
LatticeXP2 High-Speed I/O Interface
P2
N2
P2
N3
P3
N2
N2
P3
N3
P4
N4
P3
N3
N3
P4
Q
N4
..
..
P4