LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 168

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Each EBR block consists of 18,432 bits of RAM. The values for x’s (for address) and y’s (data) for each EBR block
for the devices are as in Table 10-9.
Table 10-9. Pseudo-Dual Port Memory Sizes for 16K Memory for LatticeXP2
Table 10-10 shows the various attributes available for the Pseudo-Dual Port Memory (RAM_DP). Some of these
attributes are user-selectable through the IPexpress GUI. For detailed attribute definitions, refer to Appendix A.
Table 10-10. Pseudo-Dual Port RAM Attributes for LatticeXP2
Read Port Address
Depth
Read Port Data Width
Write Port Address
Depth
Write Port Data Width
Write Port Enable Out-
put Registers
Enable GSR
Reset Mode
Memory File Format
Read Port Write Mode
Write Port Write Mode
Chip Select Decode for
Read Port
Chip Select Decode for
Write Port
Init Value
Pseudo-Dual
Port Memory
512 x 36
16K x 1
1K x 18
8K x 2
4K x 4
2K x 9
Size
Attribute
Input Data
DIA[17:0]
DIA[35:0]
DIA[1:0]
DIA[3:0]
DIA[8:0]
Port A
DIA
Address Depth
Read Port
Data Word Width
Read Port
Address Depth Write
Port
Data Word Width
Write Port
Register Mode
(Pipelining) for Write
Port
Enables Global Set
Reset
type
Read / Write Mode
for Read Port
Read / Write Mode
for Write Port
Chip Select Decode
for Read Port
Chip Select Decode
for Write Port
Initialization value
Selects the Reset
Description
Input Data
DIB[17:0]
DIB[35:0]
DIB[1:0]
DIB[3:0]
DIB[8:0]
Port B
DIB
16K, 8K, 4K, 2K, 1K, 512
1, 2, 4, 9, 18, 36
16K, 8K, 4K, 2K, 1K
1, 2, 4, 9, 18, 36
NOREG, OUTREG
ENABLE, DISABLE
ASYNC, SYNC
BINARY, HEX, ADDRESSED
HEX
NORMAL
NORMAL
0b000, 0b001, 0b010, 0b011,
0b100, 0b101, 0b110, 0b111
0b000, 0b001, 0b010, 0b011,
0b100, 0b101, 0b110, 0b111
0x0000000000000000000000000
000000000000000000000000000
000000000000000000000000000
0......0xFFFFFFFFFFFFFFFFFFF
FFFFFFFFFFFFFFFFFFFFFFFF
FFFFFFFFFFFFFFFFFFFFFFFF
FFFFFFFFFFFFF
Output Data
DOA[17:0]
DOA[35:0]
DOA[1:0]
DOA[3:0]
DOA[8:0]
Port A
10-18
DOA
Values
Output Data
DOB[17:0]
DOB[35:0]
DOB[1:0]
DOB[3:0]
DOB[8:0]
Port B
DOB
LatticeXP2 Memory Usage Guide
1
1
NOREG
ENABLE
ASYNC
NORMAL
NORMAL
0b000
0b000
0x000000000000
00000000000000
00000000000000
00000000000000
00000000000000
000000000000
Default Value
Read Address
[MSB:LSB]
RAD[13:0]
RAD[12:0]
RAD[11:0]
RAD[10:0]
RAD[9:0]
RAD[8:0]
Port A
Through IPexpress
User Selectable
Write Address
[MSB:LSB]
WAD[13:0]
WAD[12:0]
WAD[11:0]
WAD[10:0]
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
WAD[9:0]
WAD[8:0]
NO
NO
NO
Port B