UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 784

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note It is used as the clock output of the flash programmer for MINICUBE2. For details, see CHAPTER 28 FLASH
Remark GC: 100-pin plastic LQFP (fine pitch) (14 × 14)
29.2.2 Maskable functions
below.
784
Signal Name
SI/RxD
SO/TxD
SCK
CLK
RESET_OUT Output
FLMD0
FLMD1
HS
GND
RESET_IN
Only reset signals can be masked.
The maskable functions with the debugger (ID850QB) and the corresponding V850ES/JG3-L functions are listed
Note
MEMORY.
Pin Configuration of MINICUBE2 (QB-MINI2)
GF: 100-pin plastic LQFP (14 × 20)
Output
Output
Output
Output
Input
Input
Input
Output
I/O
−
NMI0
NMI1
NMI2
STOP
HOLD
RESET
WAIT
Pin to receive commands and data
from V850ES/JG3-L
Pin to transmit commands and data
to V850ES/JG3-L
Clock output pin for 3-wire serial
communication
Clock output pin to V850ES/JG3-L
Reset output pin to V850ES/JG3-L
Output pin to set V850ES/JG3-L to
debug mode or programming mode
Output pin to set programming mode PDL5/FLMD1 76 78 PDL5/FLMD1 76 78 PDL5/FLMD1 76 78
Handshake signal for CSI0 + HS
communication
Ground
Reset input pin on the target system
Maskable Functions with ID850QB
Table 29-3. Wiring Between V850ES/JG3-L and MINICUBE2
Pin Function
CHAPTER 29 ON-CHIP DEBUG FUNCTION
Preliminary User’s Manual U18953EJ1V0UD
Table 29-4. Maskable Functions
RESET
P41/SOB0
P40/SIB0
P42/SCKB0
Not
needed
Not
needed
FLMD0
PCM0/WAIT
V
AV
EV
SS
Pin Name
SS
SS
Reset signal generation by RESET pin input
With CSIB0-HS
Corresponding V850ES/JG3-L Functions
Note
Note
GC GF
Pin No.
33,
23 25 P911/SOB3
22 24 P910/SIB3
24 26 P912/SCKB3 55 57 Not needed
14 16 RESET
61 63 PCM0/WAIT
11 13 V
69
−
−
8
2
35,
10 FLMD0
71
− Not
− Not
4 AV
needed
needed
EV
SS
Pin Name
−
−
−
−
−
−
SS
SS
With CSIB3-HS
Note
Note
Pin No.
GC GF
33,
54 56 P30/TXDA0
53 55 P31/RXDA0
14 16 RESET
61 63 Not needed
11 13 V
69
−
−
8 10 FLMD0
2
35,
71
− Not
− Not
4 AV
needed
needed
EV
SS
Pin Name
SS
SS
With UARTA0
Note
Note
Pin No.
GC GF
33,
25 27
26 28
14 16
11 13
69
−
−
−
8
−
2
35,
10
71
−
−
−
−
4