UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 483

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.6.4 SBF reception
UAnCTL0.UAnRXE bit to 1.
bit detection is performed.
rate.
complete interrupt request signal (INTUAnR) is output. The UAnOPT0.UAnSRF bit is automatically cleared and SBF
reception ends. Error detection for the UAnSTR.UAnOVE, UAnSTR.UAnPE, and UAnSTR.UAnFE bits is suppressed
and UART communication error detection processing is not performed. Moreover, data transfer of the UARTAn
reception shift register and UAnRX register is not performed and FFH, the initial value, is held. If the SBF width is 10
or fewer bits, reception is terminated as error processing without outputting an interrupt, and the SBF reception mode
is returned to. The UAnSRF bit is not cleared at this time.
The reception enabled status is achieved by setting the UAnCTL0.UAnPWR bit to 1 and then setting the
The SBF reception wait status is set by setting the SBF reception trigger (UAnOPT0.UAnSTR bit) to 1.
In the SBF reception wait status, similarly to the UART reception wait status, the RXDAn pin is monitored and start
Following detection of the start bit, reception is started and the internal counter counts up according to the set baud
When a stop bit is received, if the SBF width is 11 or more bits, normal processing is judged and a reception
Cautions 1. If SBF is transmitted during a data reception, a framing error occurs.
(a) Normal SBF reception (detection of stop bit in more than 10.5 bits)
(b) SBF reception error (detection of stop bit in 10.5 or fewer bits)
2. Do not set the SBF reception trigger bit (UAnSRT) and SBF transmission trigger bit (UAnSTT)
INTUAnR
interrupt
RXDAn
UAnSRF
to 1 during an SBF reception (UAnSRF = 1).
RXDAn
UAnSRF
INTUAnR
interrupt
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
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Preliminary User’s Manual U18953EJ1V0UD
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Figure 15-9. SBF Reception
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10.5
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