UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 353

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Operation timing in one-shot pulse output mode
External trigger input
(only when software
INTTQ0CC0 signal
INTTQ0CCk signal
TQ0CCR0 register
TQ0CCRk register
TOQ00 pin output
TOQ0k pin output
(TIQ00 pin input)
(a) Note on rewriting TQ0CCRm register
trigger is used)
16-bit counter
To change the set value of the TQ0CCRm register to a smaller value, stop counting once, and then change
the set value.
If the value of the TQ0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
When the TQ0CCR0 register is rewritten from D
D
greater than D
greater than D
and compared with the count value. The counter counts up to FFFFH and then counts up again from
0000H. When the count value matches D
TOQ0k pin. When the count value matches D
the TOQ0k pin, and stops counting.
Therefore, the counter may output a pulse with a delay period or active period different from that of the
one-shot pulse that is originally expected.
Remark
TQ0CE bit
00
> D
FFFFH
0000H
01
and D
k = 1 to 3
01
k1
k0
and less than D
and less than D
> D
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
Delay
k1
(D
, if the TQ0CCRk register is rewritten when the count value of the 16-bit counter is
k0
)
Active level width
D
(D
k0
0
Preliminary User’s Manual U18953EJ1V0UD
− D
D
k0
00
D
k0
k0
, each set value is reflected as soon as the register has been rewritten
D
00
+ 1)
00
and if the TQ0CCR0 register is rewritten when the count value is
k1
, the counter generates the INTTQ0CCk signal and asserts the
01
(10000H + D
, the counter generates the INTTQ0CC0 signal, deasserts
D
00
k0
to D
Delay
01
and the TQ0CCRk register from D
D
k1
00
)
Active level width
(D
D
01
k1
− D
k1
D
k1
+ 1)
D
01
D
01
Delay
(D
k1
D
)
Active level width
k1
(D
01
k0
− D
to D
D
k1
01
+ 1)
k1
where
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