UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 664

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.3.2 Restore
address of the restored PC.
664
Recovery from maskable interrupt servicing is carried out by the RETI instruction.
When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the
<1> Loads the restored PC and PSW from EIPC and EIPSW because the PSW.EP bit is 0 and the PSW.NP bit is
<2> Transfers control back to the address of the restored PC and PSW.
The processing of the RETI instruction is shown below.
Note For the ISPR register, see 19.3.6 In-service priority register (ISPR).
Caution When the EP and NP bits are changed by the LDSR instruction during maskable interrupt
Remark
0.
servicing, in order to restore the PC and PSW correctly during recovery by the RETI
instruction, it is necessary to set the EP bit back to 0 and the NP bit back to 0 using the LDSR
instruction immediately before the RETI instruction.
The solid line shows the CPU processing flow.
1
PC
PSW
Corresponding
bit of ISPR
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Restores original processing
RETI instruction
Note
Figure 19-6. RETI Instruction Processing
PSW.EP
PSW.NP
Preliminary User’s Manual U18953EJ1V0UD
0
0
EIPC
EIPSW
0
1
PC
PSW
FEPC
FEPSW