UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 206

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.5.3
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(1) When PLL is used
(2) When PLL is not used
• After the reset signal has been released, the PLL operates (PLLCTL.PLLON bit = 1), but because the default
• To enable PLL operation, first set the PLLON bit to 1, and then set the SELPLL bit to 1 after the
• The PLL stops during transition to the IDLE2 or STOP mode regardless of the setting and is restored from
• The clock-through mode (SELPLL bit = 0) is selected after the reset signal has been released, but the PLL is
Usage
mode is the clock-through mode (PLLCTL.SELPLL bit = 0), select the PLL mode (SELPLL bit = 1).
LOCKR.LOCK bit = 0. To stop the PLL, first select the clock-through mode (SELPLL bit = 0), wait for 8
clocks or more, and then stop the PLL (PLLON bit = 0).
the IDLE2 or STOP mode to the status before transition. The time required for restoration is as follows.
When transiting to the IDLE1 mode, the PLL does not stop. Stop the PLL if necessary.
operating (PLLON bit = 1) and must therefore be stopped (PLLON bit = 0).
The times required for restoration from the IDLE2 and STOP modes are as follows.
(a) When transiting to the IDLE2 or STOP mode from the clock through mode
(b) When transiting to the IDLE 2 or STOP mode while remaining in the PLL operation mode
• STOP mode: Set the OSTS register so that the oscillation stabilization time is at least 1 ms.
• IDLE2 mode: Set the OSTS register so that the setup time is at least 350
• STOP mode: Set the OSTS register so that the oscillation stabilization time is at least 1 ms.
• IDLE2 mode: Set the OSTS register so that the setup time is at least 350
• STOP mode: Set the OSTS register so that the oscillation stabilization time is at least 1 ms.
• IDLE2 mode: Set the OSTS register so that the setup time is at least 800
CHAPTER 6 CLOCK GENERATION FUNCTION
Preliminary User’s Manual U18953EJ1V0UD
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