UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 713

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

status in the low-voltage subclock operation mode.
(1) Procedure for setting “subclock operation mode” → “low-voltage subclock operation mode”
Table 21-11 shows the operating status in the subclock operation mode and Table 21-12 shows the operating
Make the following settings in the subclock operation mode.
<1> Stop the main clock and PLL.
<2> Stop the functions that are specified to be stopped in Table 21-14 Operating Status in Low-Voltage
<3> Disable the DMA operation (if the DMA operation is enabled).
<4> • Disable the maskable interrupt by the DI instruction.
<5> Write C9H (enabling data) to the REGPR register.
<6> Write 02H to the REGOVL0 register.
<7> Write 00H (protection data) to the REGPR register.
<8> As necessary, enable the maskable interrupt, NMI interrupt, or INTWDT2 interrupt by the EI instruction
Be sure to observe the above sequence.
For the setting of the subclock operation mode, see 21.7.1 Setting and operation status.
Sub-IDLE Mode.
Be especially sure to stop the following functions, because they are signals from external sources.
• Stop the SCKBn input clock when the SCKBn input clock to CSIBn is selected (n = 0 to 4).
• Stop the ASCKA0 input clock when the ASCKA0 input clock to UARTA0 is selected.
• Disable the NMI interrupt (INTF02 = 0, INTR02 = 0).
• Create a status in which the INTWDT2 signal is not generated (create a status in which the INTWDT2
At this time, the output voltage of the regulator is at the low level, decreasing power consumption to an
extremely low level.
(restore the setting <4> above).
signal is not generated immediately after watchdog timer 2 has been cleared).
CHAPTER 21 STANDBY FUNCTION
Preliminary User’s Manual U18953EJ1V0UD
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