UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 472
UPD70F3737GC-UEU-AX
Manufacturer Part Number
UPD70F3737GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3737GC-UEU-AX.pdf
(861 pages)
Specifications of UPD70F3737GC-UEU-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Speed
20MHz
Number Of I /o
84
Core Processor
RISC
Program Memory Type
FLASH
Ram Size
8K x 8
Program Memory Size
128KB (128K x 8)
Data Converters
A/D 12x10b, D/A 2x8b
Oscillator Type
Internal
Peripherals
DMA, LVD, PWM, WDT
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3737GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(2) UARTAn control register 1 (UAnCTL1)
(3) UARTAn control register 2 (UAnCTL2)
Remark
For details, see 15.7 (2) UARTAn control register 1 (UAnCTL1).
For details, see 15.7 (3) UARTAn control register 2 (UAnCTL2).
For details of parity, see 15.6.9 Parity types and operations.
• This register is rewritten only when the UAnPWR bit = 0 or the UAnTXE bit = the
• If “Reception with 0 parity” is selected during reception, a parity check is not performed.
• When transmission and reception are performed in the LIN format, clear the
• This register can be rewritten only when the UAnPWR bit = 0 or the UAnTXE bit =
• When transmission and reception are performed in the LIN format, set the UAnCL
This register can be rewritten only when the UAnPWR bit = 0 or the UAnTXE bit =
the UAnRXE bit = 0.
• This register can be rewritten only when the UAnPWR bit = 0 or the UAnTXE bit =
• When transmission and reception are performed in the LIN format, set the UAnDIR
UAnPS1
UAnDIR
UAnCL
UAnSL
UAnRXE bit = 0.
Therefore, the UAnSTR.UAnPE bit is not set.
UAnPS1 and UAnPS0 bits to 00.
the UAnRXE bit = 0.
bit to 1.
the UAnRXE bit = 0.
bit to 1.
0
1
0
1
0
1
0
0
1
1
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
7 bits
8 bits
1 bit
2 bits
MSB-first transfer
LSB-first transfer
UAnPS0
Specification of data character length of 1 frame of transmit/receive data
0
1
0
1
Parity selection during transmission Parity selection during reception
Preliminary User’s Manual U18953EJ1V0UD
No parity output
0 parity output
Odd parity output
Even parity output
Specification of length of stop bit for transmit data
Transfer direction selection
Reception with no parity
Reception with 0 parity
Odd parity check
Even parity check
(2/2)
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