UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 183

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.7
cycle that is executed for each space selected by the memory block in the multiplex address/data bus mode. In the
separate bus mode, one idle state (TI) can be inserted after the T2 state. By inserting an idle state, the data output
float delay time of the memory can be secured during read access (an idle state cannot be inserted during write
access).
To facilitate interfacing with low-speed memories, one idle state (TI) can be inserted after the T3 state in the bus
Whether the idle state is to be inserted can be programmed by using the BCC register.
An idle state is inserted for all the areas immediately after system reset.
(1) Bus cycle control register (BCC)
Idle State Insertion Function
The BCC register can be read or written in 16-bit units.
Reset sets this register to AAAAH.
Cautions 1. The internal ROM, internal RAM, and on-chip peripheral I/O areas are not subject to idle
Caution Be sure to set bits 15, 13, 11, and 9 to “1”, and clear bits 14, 12, 10, 8, 6, 4, 2, and 0 to “0”.
After reset:
2. Write to the BCC register after reset, and then do not change the set values. Also, do not
BCC
state insertion.
access an external memory area until the initial settings of the BCC register are complete.
Memory block 3
BC31
BCn1
15
AAAAH
1
0
1
7
Not inserted
Inserted
14
0
6
0
CHAPTER 5 BUS CONTROL FUNCTION
R/W
Memory block 2
Preliminary User’s Manual U18953EJ1V0UD
Specifies insertion of idle state (n = 0 to 3)
BC21
13
1
5
Address:
FFFFF48AH
12
0
4
0
Memory block 1
BC11
11
1
3
10
0
2
0
Memory block 0
BC01
1
9
1
0
0
8
0
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