UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 165
UPD70F3737GC-UEU-AX
Manufacturer Part Number
UPD70F3737GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3737GC-UEU-AX.pdf
(861 pages)
Specifications of UPD70F3737GC-UEU-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Speed
20MHz
Number Of I /o
84
Core Processor
RISC
Program Memory Type
FLASH
Ram Size
8K x 8
Program Memory Size
128KB (128K x 8)
Data Converters
A/D 12x10b, D/A 2x8b
Oscillator Type
Internal
Peripherals
DMA, LVD, PWM, WDT
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number:
UPD70F3737GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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4.6.2
of the output latch of an input port that is not subject to manipulation may be written in addition to the targeted bit.
P91 to P97
When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value
Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode.
<Example>
Port 9L latch
0
Cautions on bit manipulation instruction for port n register (Pn)
P90
0
0
When P90 pin is an output port, P91 to P97 pins are input ports (all pin statuses are high level), and
the value of the port latch is 00H, if the output of P90 pin is changed from low level to high level via
a bit manipulation instruction, the value of the port latch is FFH.
Explanation: The targets of writing to and reading from the Pn register of a port whose PMnm bit is
1 are the output latch and pin status, respectively.
A bit manipulation instruction is executed in the following order in the V850ES/JG3-L.
<1> The Pn register is read in 8-bit units.
<2> The targeted one bit is manipulated.
<3> The Pn register is written in 8-bit units.
In step <1>, the value of the output latch (0) of P90 pin, which is an output port, is read, while the
pin statuses of P91 to P97 pins, which are input ports, are read. If the pin statuses of P91 to P97
pins are high level at this time, the read value is FEH.
The value is changed to FFH by the manipulation in <2>.
FFH is written to the output latch by the manipulation in <3>.
0
Pin status: High level
Bit manipulation instruction for P90 bit
<1> P9L register is read in 8-bit units.
<2> Set (1) P90 bit.
<3> Write the results of <2> to the output latch of P9L register in 8-bit units.
Low-level output
0
Figure 4-35. Bit Manipulation Instruction (P90 Pin)
• In the case of P90, an output port, the value of the port latch (0) is read.
• In the case of P91 to P97, input ports, the pin status (1) is read.
0
0
Preliminary User’s Manual U18953EJ1V0UD
CHAPTER 4 PORT FUNCTIONS
0
Bit manipulation
instruction
(set1 0, P9L[r0])
is executed for
P90 bit.
P91 to P97
Port 9L latch
1
P90
1
1
1
Pin status: High level
High-level output
1
1
1
1
165
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