UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 378

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

378
(b) Pulse width measurement with capture register
When pulse width measurement is performed with the TQ0CCRm register used as a capture register,
software processing is necessary for reading the capture register each time the INTTQ0CCm signal has
been detected and for calculating an interval.
INTTQ0CC0 signal
TQ0CCR0 register
INTTQ0CC1 signal
INTTQ0CC2 signal
INTTQ0CC3 signal
TQ0CCR1 register
TQ0CCR2 register
TQ0CCR3 register
INTTQ0OV signal
TIQ00 pin input
TIQ01 pin input
TIQ02 pin input
TIQ03 pin input
16-bit counter
TQ0OVF bit
TQ0CE bit
FFFFH
0000H
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
Pulse interval
(D
Pulse interval
20
(D
Pulse interval
Pulse interval
0000
0000
0000
0000
00
+ 1)
(D
(D
+ 1)
D
30
10
Preliminary User’s Manual U18953EJ1V0UD
20
D
+ 1)
+ 1)
00
D
30
Pulse interval
D
(10000H +
D
10
D
01
Pulse interval
Pulse interval
CLR instruction
Cleared to 0 by
(10000H +
Pulse interval
00
(10000H +
− D
D
D
(10000H +
11
21
D
D
00
31
D
D
− D
− D
20
)
01
10
− D
D
10
30
20
)
D
)
30
Pulse interval
11
)
D
(10000H +
D
Pulse interval
21
02
(10000H +
D
D
D
− D
12
31
01
− D
Cleared to 0 by
CLR instruction
D
01
Pulse interval
11
)
(10000H +
11
D
D
)
32
12
Pulse interval
D
D
− D
(20000H +
Pulse interval
31
02
D
(D
22
31
Pulse interval
D
D
13
D
)
− D
(10000H +
21
D
12
32
− D
D
03
21
13
D
− D
12
)
Cleared to 0 by
CLR instruction
02
)
Pulse interval
02
(10000H +
)
D
D
33
03
D
Pulse interval
− D
D
22
(D
32
32
23
D
D
)
13
− D
33
D
D
22
D
23
22
03
)
D
33
D
23