UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 258

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

258
(2) Operation timing in one-shot pulse output mode
External trigger input
(only when software
INTTPnCC0 signal
INTTPnCC1 signal
TPnCCR0 register
TPnCCR1 register
TOPn0 pin output
TOPn1 pin output
(a) Note on rewriting TPnCCRm register
(TIPn0 pin input)
trigger is used)
16-bit counter
To change the set value of the TPnCCRm register to a smaller value, stop counting once, and then change
the set value.
If the value of the TPnCCRm register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
When the TPnCCR0 register is rewritten from D
D
greater than D
than D
compared with the count value. The counter counts up to FFFFH and then counts up again from 0000H.
When the count value matches D
pin. When the count value matches D
TOPn1 pin, and stops counting.
Therefore, the counter may output a pulse with a delay period or active period different from that of the
one-shot pulse that is originally expected.
Remark
00
TPnCE bit
> D
FFFFH
0000H
01
01
and less than D
and D
n = 0 to 5
m = 0, 1
11
10
and less than D
> D
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
11
, if the TPnCCR1 register is rewritten when the count value of the 16-bit counter is
00
Delay
(D
, each set value is reflected as soon as the register has been rewritten and
10
D
Preliminary User’s Manual U18953EJ1V0UD
)
10
Active level width
(D
10
11
00
and if the TPnCCR0 register is rewritten when the count value is greater
D
, the counter generates the INTTPnCC1 signal and asserts the TOPn1
− D
00
10
01
+ 1)
D
, the counter generates the INTTPnCC0 signal, deasserts the
10
D
Delay
(D
00
00
10
D
)
10
to D
Active level width
(D
00
D
01
− D
00
and the TPnCCR1 register from D
10
+ 1)
D
10
Delay
(10000H + D
D
00
11
)
D
D
D
Active level width
(D
11
11
01
D
01
01
− D
10
11
to D
+ 1)
11
where