UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 488

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.6.8 Reception errors
reception result error flags are set in the UAnSTR register and a reception complete interrupt request signal
(INTUAnR) is output when an error occurs.
488
Errors during a receive operation are of three types: parity errors, framing errors, and overrun errors. Data
It is possible to ascertain which error occurred during reception by reading the contents of the UAnSTR register.
Clear the reception error flag by writing 0 to it after reading it.
• Receive data read flow
Caution When an INTUAnR signal is generated, the UAnSTR register must be read to check for errors.
• Reception error causes
UAnPE
UAnFE
UAnOVE
Error Flag
Parity error
Framing error
Overrun error
Reception Error
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
Preliminary User’s Manual U18953EJ1V0UD
Received parity bit does not match the setting
Stop bit not detected
Reception of next data completed before data was read from receive buffer
Read UAnSTR register
Read UAnRX register
INTUAnR signal
Error processing
Error occurs?
generated?
START
END
Yes
Yes
No
No
Cause