UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 179

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.6
5.6.1
(1) Data wait control register 0 (DWC0)
Wait Function
To realize interfacing with a low-speed memory or I/O, up to seven data wait states can be inserted in the bus
cycle that is executed for each memory block space.
The number of wait states can be programmed by using the DWC0 register . Immediately after system reset, 7
data wait states are inserted for all the blocks.
The DWC0 register can be read or written in 16-bit units.
Reset sets this register to 7777H.
Cautions 1. The internal ROM and internal RAM areas are not subject to programmable wait, and are
Caution Be sure to clear bits 15, 11, 7, and 3 to “0”.
Programmable wait function
DWC0
2. Write to the DWC0 register after reset, and then do not change the set values. Also, do
After reset:
always accessed without a wait state. The on-chip peripheral I/O area is also not subject
to programmable wait, and only wait control from each peripheral function is performed.
not access an external memory area until the initial settings of the DWC0 register are
complete.
DWn2
15
7777H
0
7
0
0
0
0
0
1
1
1
1
DW32
DW12
DWn1
14
0
0
1
1
0
0
1
1
6
R/W
CHAPTER 5 BUS CONTROL FUNCTION
Memory block 3
Memory block 1
Preliminary User’s Manual U18953EJ1V0UD
DW31
DW11
DWn0
Address:
13
5
0
1
0
1
0
1
0
1
DW30
DW10
None
1
2
3
4
5
6
7
FFFFF484H
12
4
memory block n space (n = 0 to 3)
Number of wait states inserted in
11
0
3
0
DW22
DW02
10
2
Memory block 0
Memory block 2
DW21
DW01
9
1
DW20
DW00
8
0
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