UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 40

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2.2
40
P05/DRST
P10/ANO0,
P11/ANO1
P53/DDO
AD0 to AD15
A0 to A15
A16 to A21
WAIT
CLKOUT
WR0, WR1
RD
ASTB
HLDAK
HLDRQ
Other port pins
The operation states of pins in the various modes are described below.
Notes 1. Duration until 1 ms elapses after the supply voltage reaches the operating supply voltage range (lower
Remark
Pin Name
Pin States
2. Operates while an alternate function is operating.
3. In separate bus mode, the state of the pins in the idle state inserted after the T2 state is shown. In
4. Pulled down during external reset. During internal reset by the watchdog timer, clock monitor, etc., the
5. DDO output is specified in the on-chip debug mode.
6. The bus control pins function alternately as port pins, so they are initialized to the input mode (port
7. Operates even in the HALT mode, during DMA operation.
8. In separate bus mode: Hi-Z
9. In separate bus mode
limit) when the power is turned on.
multiplexed bus mode, the state of the pins in the idle state inserted after the T3 state is shown.
state of this pin differs according to the OCDM.OCDM0 bit setting.
mode).
In multiplexed bus mode: Undefined
Hi-Z: High impedance
Held: The state during the immediately preceding external bus cycle is held.
L:
H:
−:
When Power
Pulled down
Undefined
Low-level output
High-level output
Input without sampling (not acknowledged)
Is Turned
Hi-Z
On
Hi-Z
Note 1
Note 6
Table 2-2. Pin Operation States in Various Modes
Pulled down
(Except When
During Reset
Turned On)
Power Is
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Note 5
Note 6
Preliminary User’s Manual U18953EJ1V0UD
Note 4
CHAPTER 2 PIN FUNCTIONS
Undefined
HALT Mode
Undefined
Operating
Notes 7, 8
Operating
H
Held
Held
Held
Held
Note 7
−
Notes 7, 9
Note 7
Note 7
Note 2
IDLE1, IDLE2,
Sub-IDLE
Mode
Held
Held
Held
Held
Hi-Z
H
−
L
−
Note 2
Mode
STOP
Held
Held
Held
Hi-Z
Hi-Z
H
−
L
−
Note 2
Operating
State
Held
Held
Held
Held
Held
Idle
H
−
−
Note 3
Operating
Operating
Bus Hold
Held
Held
Held
Held
Hi-Z
Hi-Z
−
L