UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 242

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16-bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from
the TOPn1 pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and
restarted. (The output of the TOPn0 pin is inverted. The TOPn1 pin outputs a high-level regardless of the status
(high/low) when a trigger occurs.)
count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare
match interrupt request signal INTTPnCC1 is generated when the count value of the 16-bit counter matches the value
of the CCR1 buffer register.
bit counter matches the value of the CCRm buffer register and the 16-bit counter is cleared to 0000H.
as the trigger.
242
16-bit timer/event counter P waits for a trigger when the TPnCE bit is set to 1. When the trigger is generated, the
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
The compare match request signal INTTPnCC0 is generated when the 16-bit counter counts next time after its
The value set to the TPnCCRm register is transferred to the CCRm buffer register when the count value of the 16-
The valid edge of an external trigger input signal, or setting the software trigger (TPnCTL1.TPnEST bit) to 1 is used
Remark
External trigger input
(only when software
INTTPnCC0 signal
INTTPnCC1 signal
TPnCCR0 register
TPnCCR1 register
Active level width = (Set value of TPnCCR1 register) × Count clock cycle
Cycle = (Set value of TPnCCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TPnCCR1 register)/(Set value of TPnCCR0 register + 1)
TOPn0 pin output
TOPn1 pin output
(TIPn0 pin input)
trigger is used)
16-bit counter
TPnCE bit
n = 0 to 5, m = 0, 1
FFFFH
0000H
Figure 7-17. Basic Timing in External Trigger Pulse Output Mode
trigger
Wait
for
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
Active level
width (D
Cycle (D
D
Preliminary User’s Manual U18953EJ1V0UD
1
1
)
D
0
0
+ 1)
Active level
width (D
Cycle (D
D
1
1
)
D
0
0
+ 1)
D
D
0
1
D
1
D
0
Active level
width (D
Cycle (D
D
1
1
)
D
0
0
+ 1)