UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 184

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.8
5.8.1
external address/data bus goes into a high-impedance state and is released (bus hold status). If the request for the
bus mastership is cleared and the HLDRQ pin is deasserted (high level), driving these pins is started again.
on-chip peripheral I/O register or the external memory is accessed.
configuration of multi-processor type systems in which two or more bus masters exist.
function or a bit manipulation instruction.
184
CPU bus lock
Read-modify-write access of bit
manipulation instruction
The HLDRQ and HLDAK functions are valid if the PCM2 and PCM3 pins are set to alternate function.
When the HLDRQ pin is asserted (low level), indicating that another bus master has requested bus mastership, the
During the bus hold period, execution of the program in the internal ROM and internal RAM is continued until an
The bus hold status is indicated by assertion of the HLDAK pin (low level). The bus hold function enables the
Note that the bus hold request is not acknowledged during a multiple-access cycle initiated by the bus sizing
Bus Hold Function
Functional outline
Status
Data Bus
16 bits
8 bits
Width
−
CHAPTER 5 BUS CONTROL FUNCTION
Preliminary User’s Manual U18953EJ1V0UD
Word access to even address
Word access to odd address
Halfword access to odd address
Word access
Halfword access
Access Type
−
Between first and second access
Between first and second access
Between second and third access
Between first and second access
Between first and second access
Between second and third access
Between third and fourth access
Between first and second access
Between read access and write
access
Timing at Which Bus Hold Request
Is Not Acknowledged