UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 387

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

later detected, the count value of the 16-bit counter is stored in the TQ0CCRm register, the 16-bit counter is cleared to
0000H, and a capture interrupt request signal (INTTQ0CCm) is generated.
interrupt request signal (INTTQ0OV) is generated at the next count clock, and the counter is cleared to 0000H and
continues counting. At this time, the overflow flag (TQ0OPT0.TQ0OVF bit) is also set to 1. Clear the overflow flag to 0
by executing the CLR instruction via software.
When the TQ0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIQ0m pin is
The pulse width is calculated as follows.
If the valid edge is not input to the TIQ0m pin even when the 16-bit counter counted up to FFFFH, an overflow
If the overflow flag is set to 1, the pulse width can be calculated as follows.
Remark
Pulse width = Captured value × Count clock cycle
Pulse width = (10000H × TQ0OVF bit set (1) count + Captured value) × Count clock cycle
INTTQ0CCm signal
TQ0CCRm register
Remark
INTTQ0OV signal
TIQ0m pin input
m = 0 to 3
16-bit counter
TQ0OVF bit
TQ0CE bit
FFFFH
0000H
m = 0 to 3
Figure 8-35. Basic Timing in Pulse Width Measurement Mode
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
0000H
Preliminary User’s Manual U18953EJ1V0UD
D
0
D
1
Cleared to 0 by
CLR instruction
D
2
D
3
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