UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 320

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

320
(c) Notes on rewriting TQ0CCR0 register
To change the value of the TQ0CCR0 register to a smaller value, stop counting once and then change the
set value.
If the value of the TQ0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
Remark
If the value of the TQ0CCR0 register is changed from D
less than D
has been rewritten. Consequently, the value of the 16-bit counter that is compared is D
Because the count value has already exceeded D
overflows, and then counts up again from 0000H. When the count value matches D
signal is generated and the output of the TOQ00 pin is inverted.
Therefore, the INTTQ0CC0 signal may not be generated at the interval time “(D
or “(D
+ 1) × Count clock period”.
INTTQ0CC0 signal
TQ0CCR0 register
2
TOQ00 pin output
+ 1) × Count clock cycle” originally expected, but may be generated at an interval of “(10000H + D
16-bit counter
Interval time (1):
Interval time (NG): (10000H + D
Interval time (2):
1
TQ0OL0 bit
, the count value is transferred to the CCR0 buffer register as soon as the TQ0CCR0 register
TQ0CE bit
FFFFH
0000H
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
L
Preliminary User’s Manual U18953EJ1V0UD
(D
(D
Interval time (1)
1
2
+ 1) × Count clock cycle
+ 1) × Count clock cycle
D
1
D
2
1
+ 1) × Count clock cycle
D
2
Interval time (NG)
2
, however, the 16-bit counter counts up to FFFFH,
D
1
1
to D
2
while the count value is greater than D
D
2
D
2
Interval
time (2)
D
2
1
+ 1) × Count clock cycle”
2
2
.
, the INTTQ0CC0
2
but
2